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EBJ81UG8EBU0

Description
8GB DDR3L SDRAM SO-DIMM
File Size211KB,16 Pages
ManufacturerELPIDA
Websitehttp://www.elpida.com/en
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EBJ81UG8EBU0 Overview

8GB DDR3L SDRAM SO-DIMM

DATA SHEET
8GB DDR3L SDRAM SO-DIMM
EBJ81UG8EBU0 (1024M words
×
64 bits, 2 Ranks)
Specifications
Density: 8GB
Organization
1024M words
×
64 bits, 2 ranks
Mounting 16 pieces of 4G bits DDR3L SDRAM
sealed in FBGA
Package: 204-pin socket type small outline dual
in-line memory module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant) and Halogen-free
Power supply: 1.35V (typ.)
VDD
=
1.283V to 1.45V
Backward compatible for VDD
=
1.5V
±
0.075V
Data rate: 1600Mbps/1333Mbps (max.)
Backward compatible to1066Mbps/800Mbps/667Mbps
Eight internal banks for concurrent operation
(components)
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
/CAS write latency (CWL): 5, 6, 7, 8
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles
Average refresh period
7.8µs at 0°C
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture: two data transfers per
clock cycle
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die-Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern
read out
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
/RESET pin for Power-up sequence and reset
function
SRT range:
Normal/extended
Programmable Output driver impedance control
Document No. E1812E30 (Ver. 3.0)
Date Published November 2011 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2011

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