DATA SHEET
8GB DDR3L SDRAM SO-DIMM
EBJ81UG8EBU0 (1024M words
×
64 bits, 2 Ranks)
Specifications
•
Density: 8GB
•
Organization
1024M words
×
64 bits, 2 ranks
•
Mounting 16 pieces of 4G bits DDR3L SDRAM
sealed in FBGA
•
Package: 204-pin socket type small outline dual
in-line memory module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant) and Halogen-free
•
Power supply: 1.35V (typ.)
VDD
=
1.283V to 1.45V
Backward compatible for VDD
=
1.5V
±
0.075V
•
Data rate: 1600Mbps/1333Mbps (max.)
Backward compatible to1066Mbps/800Mbps/667Mbps
•
Eight internal banks for concurrent operation
(components)
•
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
•
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
•
/CAS write latency (CWL): 5, 6, 7, 8
•
Precharge: auto precharge option for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
TC = 0°C to +95°C
Features
•
Double-data-rate architecture: two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
On-Die-Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
•
Multi Purpose Register (MPR) for pre-defined pattern
read out
•
ZQ calibration for DQ drive and ODT
•
Programmable Partial Array Self-Refresh (PASR)
•
/RESET pin for Power-up sequence and reset
function
•
SRT range:
Normal/extended
•
Programmable Output driver impedance control
Document No. E1812E30 (Ver. 3.0)
Date Published November 2011 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2011
EBJ81UG8EBU0
Pin Description
Pin name
A0 to A15
A10 (AP)
A12 (/BC)
BA0, BA1, BA2
/RAS
/CAS
/WE
/CS0, /CS1
CKE0, CKE1
CK0, CK1
/CK0, /CK1
ODT0, ODT1
DQ0 to DQ63
DQS0 to DQS7, /DQS0 to /DQS7
DM0 to DM7
SCL
SDA
SA0, SA1
VDD*
1
Function
Address input
Row address
Column address
Auto precharge
Burst chop
Bank select address
Row address strobe
Column address strobe
Write enable
Chip select
Clock enable
Clock input
Differential clock input
ODT control
Data input/output
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Address input for serial PD
Power for internal circuit
Power for serial PD
Reference voltage for CA
Reference voltage for DQ
Ground
I/O termination supply for SDRAM
Set DRAM to a known state
No connection
A0 to A15
A0 to A9
VDDSPD
VREFCA
VREFDQ
VSS
VTT
/RESET
NC
Note: 1. The VDD and VDDQ pins are tied common to a single power-plane on these designs.
Front side
1 pin
71 pin 73 pin
203 pin
2 pin
72 pin 74 pin
204 pin
Back side
Data Sheet E1812E30 (Ver. 3.0)
4
EBJ81UG8EBU0
Serial PD Matrix
-DJ
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34 to 59
Function described
Number of serial PD bytes written/SPD device
size/CRC coverage
SPD revision
Key byte/DRAM device type
Key byte/module type
SDRAM density and banks
SDRAM addressing
Module nominal voltage, VDD
Module organization
Module memory bus width
Fine timebase (FTB) dividend/divisor
Medium timebase (MTB) dividend
Medium timebase (MTB) divisor
SDRAM minimum cycle time (tCK (min.))
Reserved
SDRAM CAS latencies supported, LSB
SDRAM CAS latencies supported, MSB
SDRAM minimum CAS latencies time (tAA (min.))
SDRAM minimum write recovery time (tWR (min.))
SDRAM minimum /RAS to /CAS delay (tRCD (min.))
SDRAM minimum row active to row active delay
(tRRD (min.))
SDRAM minimum row precharge time (tRP (min.))
SDRAM upper nibbles for tRAS and tRC
SDRAM minimum active to precharge time
(tRAS (min.)), LSB
SDRAM minimum active to active /auto-refresh time
(tRC (min.)), LSB
SDRAM minimum refresh recovery time delay
(tRFC (min.)), LSB
SDRAM minimum refresh recovery time delay
(tRFC (min.)), MSB
SDRAM minimum internal write to read command
delay (tWTR (min.))
SDRAM minimum internal read to precharge
command delay (tRTP (min.))
Upper nibble for tFAW
Minimum four activate window delay time
(tFAW (min.))
SDRAM optional features
SDRAM thermal and refresh options
Module thermal sensor
SDRAM device type
Reserved
Hex
92h
10h
0Bh
03h
04h
21h
02h
09h
03h
52h
01h
08h
0Ch
00h
7Eh
00h
69h
78h
69h
30h
69h
11h
20h
89h
20h
08h
3Ch
3Ch
00h
F0h
83h
81h
00h
00h
00h
Comments
176/256/0-116
Rev.1.0
DDR3 SDRAM
SO-DIMM
4G bits, 8 banks
16 rows, 10 columns
1.5V/1.35V
2 ranks/×8 bits
64 bits/non-ECC
5/2
1
8
1.5ns
—
5, 6, 7, 8, 9, 10
—
13.125ns
15ns
13.125ns
6ns
13.125ns
—
36ns
49.125ns
260ns
260ns
7.5ns
7.5ns
30ns
30ns
DLL-off, RZQ/6, 7
PASR/2X refresh at
+85ºC to +95ºC
Not incorporated
Standard
—
-GN
Hex
92h
10h
0Bh
03h
04h
21h
02h
09h
03h
52h
01h
08h
0Ah
00h
FEh
00h
69h
78h
69h
30h
69h
11h
18h
81h
20h
08h
3Ch
3Ch
00h
F0h
83h
81h
00h
00h
00h
Comments
176/256/0-116
Rev.1.0
DDR3 SDRAM
SO-DIMM
4G bits, 8 banks
16 rows, 10 columns
1.5V/1.35V
2 ranks/x8 bits
64 bits/non-ECC
5/2
1
8
1.25ns
—
5, 6, 7, 8, 9, 10, 11
—
13.125ns
15ns
13.125ns
6ns
13.125ns
—
35ns
48.125ns
260ns
260ns
7.5ns
7.5ns
30ns
30ns
DLL-off, RZQ/6, 7
PASR/2X refresh at
+85ºC to +95ºC
Not incorporated
Standard
—
Data Sheet E1812E30 (Ver. 3.0)
5
Analogue and Mixed Signal
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