DS1323 datasheet, PDF - EEWORLD Datasheet

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DS1323: Description3.3V Flexible Nonvolatile Controller with Lithium Battery Monitor; File Size294KB，14 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1323 Overview

3.3V Flexible Nonvolatile Controller with Lithium Battery Monitor

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19-5920; Rev 6/11

DS1323

3.3V Flexible Nonvolatile Controller with

Lithium Battery Monitor

FEATURES



Converts CMOS SRAM into nonvolatile

memory

Unconditionally write-protects SRAM when

is out of tolerance

Automatically switches to battery backup

when V

power failure occurs

Flexible memory organization

- Mode 0: 4 banks with 1 SRAM each

- Mode 1: 2 banks with 2 SRAMs each

- Mode 2: 1 bank with 4 SRAMs each

Monitors voltage of a lithium cell and

provides advanced warning of impending

battery failure

Signals low-battery condition on active low

battery warning output signal

Resets processor when power failure occurs

and holds processor in reset during system

power-up

10% power-fail detection

Industrial temperature range of -40°C to

+85°C

PIN ASSIGNMENT

CCO

BAT

CEI1

CEI2

A/CEI3

B/CEI4

GND

CCI

RST

CEO1

CEO2

CEO3

CEO4

MODE



DS1323E 20-Pin TSSOP

(173 mils)

PIN DESCRIPTION

CCI

CCO

BAT

A, B

- +3.3V Power Supply Input

- SRAM Power Supply Output

- Backup Battery Input

- Address Inputs

CEI1

CEI4

- Chip Enable Inputs

CEO1

CEO4

- Chip Enable Outputs

- Battery Warning Output (Open

Drain)

- Reset Output (Open Drain)

RST

MODE

- Mode Input

GND

- Ground

- No Connection

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DS1323

DESCRIPTION

The DS1323 Flexible Nonvolatile Controller with Lithium Battery Monitor is a CMOS circuit that solves the

application problem of converting CMOS SRAMs into nonvolatile memory. Incoming power is monitored

for an out-of-tolerance condition. When such a condition is detected, chip-enable outputs are inhibited to

accomplish write protection and the battery is switched on to supply the SRAMs with uninterrupted power.

Special circuitry uses a low-leakage CMOS process which affords precise voltage detection at extremely low

battery consumption. One DS1323 can support as many as four SRAMs arranged in any of three memory

configurations.

In addition to battery-backup support, the DS1323 performs the important function of monitoring the

remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life.

Because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority of

its life, accurate battery monitoring requires loaded-battery voltage measurement. The DS1323 performs

such measurement by periodically comparing the voltage of the battery as it supports an internal resistive

load with a carefully selected reference voltage. If the battery voltage falls below the reference voltage under

such conditions, the battery will soon reach end-of-life. As a result, the battery warning pin is activated to

signal the need for battery replacement.

MEMORY BACKUP

The DS1323 performs all the circuit functions required to provide battery-backup for as many as four

SRAMs. First, the device provides a switch to direct power from the battery or the system power supply

CCI

). Whenever V

CCI

is less than the V

CCTP

trip point and V

CCI

is less than the battery voltage V

BAT

, the

battery is switched on to provide backup power to the SRAM. This switch has voltage drop of less than 0.2

volts.

Second, the DS1323 handles power failure detection and SRAM write-protection. V

CCI

is constantly

monitored, and when the supply goes out of tolerance, a precision comparator detects power failure and

inhibits the four chip enable outputs in order to write-protect the SRAMs. This is accomplished by holding

CEO1

through

CEO4

to within 0.2 volts of V

CCO

when V

CCI

is out of tolerance. If any

CEI

is active (low) at

the time that power failure is detected, the corresponding

CEO

signal is kept low until the

CEI

signal is

brought high again. Once the

CEI

signal is brought high, the

CEO

signal is taken high and held high until

after V

CCI

has returned to its nominal voltage level. If the

CEI

signal is not brought high by 1.5µs after

power failure is detected, the corresponding

CEO

is forced high at that time. This specific scheme for

delaying write protection for up to 1.5µs guarantees that any memory access in progress when power failure

occurs will complete properly. Power failure detection occurs in the range of 2.8 to 3.0 volts.

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