EEWORLDEEWORLDEEWORLD

Part Number

Search

KSK-1A54-100140

Description
KSK Reed Switch
File Size40KB,1 Pages
ManufacturerMEDER electronic ( Standex )
Websitehttps://standexelectronics.com
Download Datasheet View All

KSK-1A54-100140 Overview

KSK Reed Switch

Europe: +49 / 7733 9487 0 | Email: info@meder.com
USA:
Asia:
+1 / 508 539 0002 | Email: salesusa@meder.com
+852 / 2955 1682 | Email: salesasia@meder.com
Item No.:
Item:
2115400140
KSK-1A54-100140
Magnetical properties
Conditions
Min
Setpoint
KMS-05
Max
Unit
Pull-In excitation (Reference value)
measured in coil- "define operation"
Test-Coil
Reed switch unmodified
Contact data 54
Contact-No.
Contact-form
Contact-material
Switching suitability
Contact rating
Switching voltage
Switching current
Carry current
Contact resistance static
Insulation resistance
Breakdown voltage
Operate time incl. bounce
Release time
Capacity
Conditions
Min
Setpoint
Max
Unit
54
A
Rh/Cu
RF applications
not to exceed their individual max.'s
DC or Peak AC
DC or Peak AC
DC or Peak AC
!
"
Start Value
# $ " "$
RH <45 %, 100 V test voltage
according to IEC 255-5
measured with 40% overdrive
measured with no coil excitation
@ 10 kHz
%
&
'
()
Environmental data
Shock
Vibration
Ambient temperature
Storage temperature
Soldering temperature
Conditions
1/2 sine wave duration 11ms
from 10 - 2000 Hz
Min
,
,
Setpoint
Max
'
'
-
Unit
*
*
+
+
+
max. 5 sec
Verarbeitungshinweise im Datenbuch oder bei www.meder.com beachten
Modifications in the sense of technical progress are reserved
Designed at:
Last Change at:
21.05.03
14.03.06
Designed by:
Last Change by:
SCHELLHORN
RKAMP
Approval at:
Approval at:
Approval by:
Approval by:
Version:
2
Verilog statement output question
input b; reg a; if(i) a = b; assign c = a; if i=0; then what is the value of c, should it be no value, or 0? c is of wire type, so it is not saved, so there is no output value, is this correct?...
tianma123 FPGA/CPLD
How to calculate the gate count of FPGA?
I often hear that FPGAs have tens of thousands of gates, but isn't the size of an FPGA measured in logic units? Is there any relationship between the two? How do you estimate tens of thousands of gate...
心仪 FPGA/CPLD
Check out Xilinx's latest release of Targeted Design Platform domain-specific kits
Here are the pictures. It's too late, and there's nothing much to write. Just a brief explanation will suffice. If I remember anything else, I'll continue to add.This is the Spartan-6 development boar...
凯哥 FPGA/CPLD
ADC12, the GND level reading is too large when the speed is fast.
The MCU I use is F5438A, the master clock is 32M. The configuration of ADC12 is master clock, 8-bit resolution, 64 sampling clocks, A0A1A2A3 round sequence; The phenomena that occur are: 1. When I use...
shushu Microcontroller MCU
PCB leakage problem
When the PCB wiring was completed, I found that a wire was missing during the missing wire check, but I couldn't find it no matter how hard I tried, and I didn't see any flying wires! :faint: Does any...
zttian PCB Design
Get the mouse idle time under wince
How can I get the idle time of the mouse in WinCE? I use a timer in the application to calculate the interval between two inputs. This method is not allowed for some reason....
hehua Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 254  912  1588  2325  2907  6  19  32  47  59 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号