7472DC datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> 7472DC

7472DC: DescriptionJbar-Kbar Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDIP14,; Categorylogic logic; File Size66KB，2 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

Download Datasheet Parametric Compare View All

7472DC Overview

Jbar-Kbar Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDIP14,

7472DC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Fairchild
package instruction	DIP, DIP14,.3
Reach Compliance Code	compliant
JESD-30 code	R-XDIP-T14
JESD-609 code	e0
Logic integrated circuit type	JBAR-KBAR FLIP-FLOP
Humidity sensitivity level	2A
Number of functions	1
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	250
Certification status	Not Qualified
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	MASTER-SLAVE

Preview

Download Datasheet

View All

This Material Copyrighted By Its Respective Manufacturer

7472DC Related Products

	7472DC	5472DM	7472FC	7472PC	54H72DMQB
Description	Jbar-Kbar Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDIP14,	Jbar-Kbar Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDIP14,	Jbar-Kbar Flip-Flop, 1-Func, Master-slave Triggered, TTL, CDFP14,	Jbar-Kbar Flip-Flop, 1-Func, Master-slave Triggered, TTL, PDIP14,	J-K Flip-Flop, TTL/H/L Series, 1-Func, Positive Edge Triggered, 2-Bit, Complementary Output, TTL, CDIP14, CERAMIC, DIP-14
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible
Reach Compliance Code	compliant	unknown	compliant	unknown	unknow
JESD-30 code	R-XDIP-T14	R-XDIP-T14	R-XDFP-F14	R-PDIP-T14	R-CDIP-T14
JESD-609 code	e0	e0	e0	e0	e0
Logic integrated circuit type	JBAR-KBAR FLIP-FLOP	JBAR-KBAR FLIP-FLOP	JBAR-KBAR FLIP-FLOP	JBAR-KBAR FLIP-FLOP	J-K FLIP-FLOP
Number of functions	1	1	1	1	1
Number of terminals	14	14	14	14	14
Maximum operating temperature	70 °C	125 °C	70 °C	70 °C	125 °C
Package body material	CERAMIC	CERAMIC	CERAMIC	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	DIP	DFP	DIP	DIP
Encapsulate equivalent code	DIP14,.3	DIP14,.3	FL14,.3	DIP14,.3	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	FLATPACK	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	250	250	250	250	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
surface mount	NO	NO	YES	NO	NO
technology	TTL	TTL	TTL	TTL	TTL
Temperature level	COMMERCIAL	MILITARY	COMMERCIAL	COMMERCIAL	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	FLAT	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	1.27 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	NOT SPECIFIED
Trigger type	MASTER-SLAVE	MASTER-SLAVE	MASTER-SLAVE	MASTER-SLAVE	POSITIVE EDGE
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	-
Maker	Fairchild	Fairchild	-	Fairchild	Fairchild
package instruction	DIP, DIP14,.3	-	DFP, FL14,.3	DIP, DIP14,.3	DIP, DIP14,.3
Humidity sensitivity level	2A	2A	2A	2A	-

Recommended Resources

Pyroelectric infrared induction automatic light circuit (7)

Power supply circuit diagram of CASPER CM-1489 dual-band monochrome display

STK463 audio IC circuit diagram

μPC1230H2 audio IC circuit diagram

Building and hotel alarm call system circuit

Safety charger circuit

Evaluation: STM32F769I-DISCO connected to Gizwits Cloud to realize IoT development remote control and other functions: Evaluation: STM32F769I-DISCO connected to Gizwits Cloud to realize IoT development remote control and other functionsAbstract: This article mainly describes how to use STM32F769I-DISCO to connect to G...; z3512641347 MCU

How does CPLD achieve frequency addition?: Recently, I tested a mature motherboard. The input signal of CPLD was 60M/8192=7.324kHZ, the clock of CPLD was 60MHZ, and the test output was 7.5M+7.324k. In CPLD, the main clock was divided by 8 and ...; qiang6091 FPGA/CPLD

The digital tube of the electronic clock is very flashing: I made an electronic clock. Why is it flashing? It seems like the voltage is unstable. I don't see this phenomenon on the bus! I don't know what's going on? ? ?...; myhmz MCU

How to generate *.bin format files in MDK: What a pity......; ljr0451 stm32/stm8

I have been stuck for 100 hours----pxa310 wince6.0 camera driver problem: I am debugging the camera driver. I am using the camera driver framework written by Marvell for Microsoft. I can already read and write registers of the ov2655 chip. When I run the camera application,...; nanhe Embedded System

TI C54xx DSP 十天速成講義: [實驗一新手上路] 初學者編寫的第一個程序通常是控制XF引腳的變化，然後用示波器測量XF腳波形或觀察與相接的LED。這個程序也常常用來測度一下DSP能否正常工作。實驗1.1 最簡單的程序：控制XF引腳週期性變化實驗目的：通過簡單的程序瞭解DSP程序的結構，熟悉CCS開發環境。 **********************************************************...; c2535103 DSP and ARM Processors

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components