EEWORLDEEWORLDEEWORLD

Part Number

Search

2200SAG100822KB

Description
Strain Guage Sensor, Absolute, 0Psi Min, 100Psi Max, 0.15%, 0-10V, Cylindrical
CategoryThe sensor    Sensor/transducer   
File Size507KB,4 Pages
ManufacturerGems Sensors & Controls
Download Datasheet Parametric View All

2200SAG100822KB Overview

Strain Guage Sensor, Absolute, 0Psi Min, 100Psi Max, 0.15%, 0-10V, Cylindrical

2200SAG100822KB Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Reach Compliance Codeunknow
Maximum accuracy(%)0.15%
shellSTAINLESS STEEL
Nominal offset0V
Maximum operating temperature80 °C
Minimum operating temperature-20 °C
Output range0-10V
Output typeANALOG VOLTAGE
Package Shape/FormCYLINDRICAL
port type1/8 NPT
Maximum pressure range100 Psi
Minimum pressure range
Pressure sensing modeABSOLUTE
Sensor/Transducer TypePRESSURE SENSOR,STRAIN GUAGE
Maximum supply voltage35 V
Minimum supply voltage1.5 V
Termination typePLASTIC CABLE GLAND
Base Number Matches1
Transformer noise
When the ADJ voltage is more than 10V, there is a squeaking noise, but when it is adjusted to about 20V, the noise disappears. Why is this happening?...
tangwei8802429 Analog electronics
Fishing alone at the canal
[b]Fishing Alone at the Canal Head[/b][color=rgb(0, 0, 0)][font=Helvetica, Arial, sans-serif]Selfie (homemade mobile phone holder installed on a homemade parasol pole) Fishing Alone at the Canal Head[...
wangfuchong Talking
I would like to ask you: The device under wince does not support overlapping IO? What is overlapping IO? ?
As the title says: Does it mean full duplex?...
naphu Embedded System
【Talk about DSP】Share my DSP development experience
[align=left][font=楷体,楷体_GB2312][size=4][color=red]I am very interested in the DSP essay solicitation activity! It has been almost a week since the activity started, but no one has participated. Is eve...
37°男人 DSP and ARM Processors
FPGA simulation and hardware debugging results
I use FPGA to run an ARM soft core and test a program to light up an LED. The simulation result is consistent with what I want (the top LED port has output), but after downloading it to the FPGA devel...
roc2 FPGA/CPLD
How to use design language to implement circuits and increase circuit speed?
1. Use parallel structure. Use pipeline method; 2. Use full synchronization design; 3. Use CASE statement instead of IF with priority ....ELSIF ....ELSIF...
eeleader FPGA/CPLD

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1805  1627  1366  658  559  37  33  28  14  12 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号