EEWORLDEEWORLDEEWORLD

Part Number

Search

TMP87CH34BN

Description
CMOS 8-BIT MICROCONTROLLER
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size7MB,139 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
Download Datasheet Parametric Compare View All

TMP87CH34BN Overview

CMOS 8-BIT MICROCONTROLLER

TMP87CH34BN Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerToshiba Semiconductor
Parts packaging codeDIP
package instructionSDIP, SDIP42,.6
Contacts42
Reach Compliance Codeunknow
Has ADCYES
Address bus width
bit size8
CPU seriesTLCS-870
maximum clock frequency8 MHz
DAC channelNO
DMA channelNO
External data bus width
JESD-30 codeR-PDIP-T42
length38 mm
Number of I/O lines33
Number of terminals42
Maximum operating temperature70 °C
Minimum operating temperature-30 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeSDIP
Encapsulate equivalent codeSDIP42,.6
Package shapeRECTANGULAR
Package formIN-LINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
RAM (bytes)1024
rom(word)16384
ROM programmabilityMROM
Maximum seat height4.5 mm
speed8 MHz
Maximum slew rate25 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelOTHER
Terminal formTHROUGH-HOLE
Terminal pitch1.778 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width15.24 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER

TMP87CH34BN Related Products

TMP87CH34BN TMP87CH34 TMP87CM34BN TMP87CK34BN
Description CMOS 8-BIT MICROCONTROLLER CMOS 8-BIT MICROCONTROLLER CMOS 8-BIT MICROCONTROLLER CMOS 8-BIT MICROCONTROLLER
Is it Rohs certified? incompatible - incompatible incompatible
Maker Toshiba Semiconductor - Toshiba Semiconductor Toshiba Semiconductor
Parts packaging code DIP - DIP DIP
package instruction SDIP, SDIP42,.6 - SDIP, SDIP42,.6 SDIP, SDIP42,.6
Contacts 42 - 42 42
Reach Compliance Code unknow - unknow unknow
Has ADC YES - YES YES
bit size 8 - 8 8
CPU series TLCS-870 - TLCS-870 TLCS-870
maximum clock frequency 8 MHz - 8 MHz 8 MHz
DAC channel NO - NO NO
DMA channel NO - NO NO
JESD-30 code R-PDIP-T42 - R-PDIP-T42 R-PDIP-T42
length 38 mm - 38 mm 38 mm
Number of I/O lines 33 - 33 33
Number of terminals 42 - 42 42
Maximum operating temperature 70 °C - 70 °C 70 °C
Minimum operating temperature -30 °C - -30 °C -30 °C
PWM channel YES - YES YES
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SDIP - SDIP SDIP
Encapsulate equivalent code SDIP42,.6 - SDIP42,.6 SDIP42,.6
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR
Package form IN-LINE, SHRINK PITCH - IN-LINE, SHRINK PITCH IN-LINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
power supply 5 V - 5 V 5 V
Certification status Not Qualified - Not Qualified Not Qualified
RAM (bytes) 1024 - 1024 1024
rom(word) 16384 - 32768 24576
ROM programmability MROM - MROM MROM
Maximum seat height 4.5 mm - 4.5 mm 4.5 mm
speed 8 MHz - 8 MHz 8 MHz
Maximum slew rate 25 mA - 25 mA 25 mA
Maximum supply voltage 5.5 V - 5.5 V 5.5 V
Minimum supply voltage 4.5 V - 4.5 V 4.5 V
Nominal supply voltage 5 V - 5 V 5 V
surface mount NO - NO NO
technology CMOS - CMOS CMOS
Temperature level OTHER - OTHER OTHER
Terminal form THROUGH-HOLE - THROUGH-HOLE THROUGH-HOLE
Terminal pitch 1.778 mm - 1.778 mm 1.778 mm
Terminal location DUAL - DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
width 15.24 mm - 15.24 mm 15.24 mm
uPs/uCs/peripheral integrated circuit type MICROCONTROLLER - MICROCONTROLLER MICROCONTROLLER
#In the Cloud#Tickets are in rush, tickets for the Cloud Computing Conference are worth 2,000 yuan!
[font=黑体][size=5][color=#ff0000]Congratulations to netizen [url=https://home.eeworld.com.cn/my/aiguodelaoge.html][b]aiguodelaoge[/b][/url] for winning a ticket to the 5th China Cloud Computing Confere...
EEWORLD社区 Embedded System
How to use D flip-flop to achieve delay???
A D flip-flop delays one CLK cycle. If it delays 10 CLK cycles, it means it triggers a few more beats. How should the program be written?StartFragmentA D flip-flop program reg A_ZRE0_CROSS_MOVE; alway...
cetc50 FPGA/CPLD
How to make Acticesync support UDP?
I am making a GPS vehicle terminal. With Acticesync, I can debug in single step. Unfortunately, I can only debug TCP protocol. I can't debug UDP because I heard that Acticesync doesn't support it. I w...
lc258 Embedded System
About transfer function
Recently, I was reading about circuit principle analysis. Regarding the transfer function, I introduced an exponential sine wave excitation to analyze the steady-state response, and finally introduced...
15272693963 Integrated technical exchanges
Learn FPGA from Teacher Xia (1) Why Verilog can support large-scale design
[flash]http://www.tudou.com/v/sYYYpxggFX0/v.swf[/flash]...
soso FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1128  592  1062  2723  2262  23  12  22  55  46 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号