November 2004
®
AS7C33512PFS18A
3.3V 512K
×
18 pipeline burst synchronous SRAM
Features
•
•
•
•
•
•
•
•
•
Organization: 524,288 words × 18 bits
Fast clock speeds to 166 MHz
Fast clock to data access: 3.5/4.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous register-to-register operation
Single-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
•
•
•
•
•
•
•
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
30 mW typical standby power in power down mode
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
CLK
CS
CLR
Burst logic
Q
19
CS
Address
register
CLK
D
19
17 19
512K × 18
Memory
array
18
18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
registers
CLK
D
2
OE
CE
CLK
ZZ
Enable
register
Q
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ[a,b]
Selection guide
–166
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.5
475
130
30
–133
7.5
133
4
425
100
30
Units
ns
MHz
ns
mA
mA
mA
11/30/04;
v.2.2
Alliance Semiconductor
1 of 20
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512PFS18A
®
8 Mb Synchronous SRAM products list
1,2
Org
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
Part Number
AS7C33512PFS18A
AS7C33256PFS32A
AS7C33256PFS36A
AS7C33512PFD18A
AS7C33256PFD32A
AS7C33256PFD36A
AS7C33512FT18A
AS7C33256FT32A
AS7C33256FT36A
AS7C33512NTD18A
AS7C33256NTD32A
AS7C33256NTD36A
AS7C33512NTF18A
AS7C33256NTF32A
AS7C33256NTF36A
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
Speed
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
NTD
1
-PL
NTD-FT
:
:
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
Pipelined Burst Synchronous SRAM with NTD
TM
Flow-through Burst Synchronous SRAM with NTD
TM
1. NTD: No Turnaround Delay. NTD
TM
is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the prop-
erty of their respective owners.
11/30/04; v.2.2
Alliance Semiconductor
2 of 20
AS7C33512PFS18A
®
Pin arrangement
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
11/30/04; v.2.2
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V
DDQ
V
SSQ
NC
NC
DQb0
DQb1
V
SSQ
V
DDQ
DQb2
DQb3
NC
V
DD
NC
V
SS
DQb4
DQb5
V
DDQ
V
SSQ
DQb6
DQb7
DQpb
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14 × 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQpa
DQa7
DQa6
V
SSQ
V
DDQ
DQa5
DQa4
VSS
NC
V
DD
ZZ
DQa3
DQa2
V
DDQ
V
SSQ
DQa1
DQa0
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
Alliance Semiconductor
3 of 20
AS7C33512PFS18A
®
Functional description
The AS7C33512PFS18A is a high performance CMOS 8-Mbit Synchronous Static Random Access Memory (SRAM) device organized as
524,288 words × 18 bits and incorporate a pipeline for highest frequency on any given technology.
Timing for this device is compatible with existing Pentium
®
synchronous cache specifications. This architecture is suited for ASIC, DSP,
and PowerPC
™1
-based systems in computing, datacom, instrumentation, and telecommunications systems.
Fast cycle times of 6/7.5 ns with clock access times (t
CD
) of 3.5/4.0 ns enable 166 and 133 MHz bus frequencies. Three chip enable inputs
permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor
address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and
driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on
all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address
strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium
®
count sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPC
™
and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW.
This device operates in single-cycle deselect feature during
read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are
as follows:
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
• Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33512PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are
available in a 100-pin 14×20 mm TQFP packaging.
.
Capacitance
Parameter
Input capacitance
I/O capacitance
*
Guaranteed not tested
Symbol
C
IN*
C
I/O*
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
Max
5
7
Unit
pF
pF
TQFP thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1 This parameter is sampled.
Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
1–layer
4–layer
Symbol
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°C/W
°C/W
°C/W
1. PowerPC
™
is a trademark International Business Machines Corporation
11/30/04; v.2.2
Alliance Semiconductor
4 of 20
AS7C33512PFS18A
®
Signal descriptions
Signal
CLK
A,A0,A1
DQ[a,b]
CE0
CE1, CE2
ADSP
ADSC
ADV
GWE
BWE
BW[a,b]
OE
LBO
ZZ
NC
I/O
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
-
Properties
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
ASYNC
-
Description
Clock. All inputs except OE, ZZ,
LBO
are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
Address strobe (processor). Asserted LOW to load a new address or to enter standby mode.
Address strobe (controller). Asserted LOW to load a new address or to enter standby mode.
Burst advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and BW[a,b]
control write enable.
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
Selects Burst mode. When tied to V
DD
or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order.
This signal is internally pulled
High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
11/30/04; v.2.2
Alliance Semiconductor
5 of 20
京公网安备 11010802033920号
EEWORLD
