K9F1208U0M-YCB0, K9F1208U0M-YIB0
Document Title
64M x 8 Bit NAND Flash Memory
Revision History
Revision No
0.0
FLASH MEMORY
History
1. Initial issue
Draft Date
Oct. 27th 2000
Remark
Advanced
Information
0.1
1. Renamed GND input (pin # 6) on behalf of SE (pin # 6)
- The SE input controls the access of the spare area. When SE is high,
the spare area is not accessible for reading or programming. SE is rec
ommended to be coupled to GND or Vcc and should not be toggled
during reading or programming.
=> Connect this input pin to GND or set to static low state unless the
sequential read mode excluding spare area is used.
2. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes into
Busy for maximum 5us.
1. Changed GND input (pin # 6) pin to N.C ( No Connection).
- The pin # 6 is don’t-cared regardless of external logic input level
and is fixed as low internally.
1. Changed plane address in Copy-Back Program
-
A24 and A25
must be the same between source and target page
=>
A14 and A15
must be the same between source and target page
1. Changed DC characteristics
Parameter
Operating
Current
Sequential Read
Program
Erase
Min
-
-
-
Typ
10
10
10
Max
20->30
20->30
20->30
mA
Unit
Dec. 5th 2000
0.2
Dec. 15th 2000
0.3
Jan. 8th 2001
0.4
Apr. 7th 2001
2. Unified access timing parameter definition for multiple operating modes
- Changed AC characteristics (Before)
Parameter
ALE to RE Delay( ID read )
CE to RE Delay( ID read)
RE Low to Status Output
CE Low to Status Output
RE access time(Read ID)
- AC characteristics (After)
. Deleted t
CR
,t
RSTO,
t
CSTO
and t
READID
/ Added t
CEA
Parameter
ALE to RE Delay( ID read )
CE Access Time
Symbol
t
AR1
t
CEA
Min
10
-
Max
-
45
Unit
ns
Symbol
t
AR1
t
CR
t
RSTO
t
CSTO
t
READID
Min
100
100
-
-
-
Max
-
-
35
45
35
ns
Unit
1
K9F1208U0M-YCB0, K9F1208U0M-YIB0
Revision History
Revision No
History
CLE
tCR
FLASH MEMORY
Draft Date
Remark
CE
WE
tAR1
ALE
RE
tREA
I/O
0
~
7
90h
00h
Address. 1cycle
ECh
Maker code
CLE
tCEA
CE
WE
tAR1
ALE
RE
I/O
0
~
7
tWHR
tREA
90h
00h
Address. 1cycle
ECh
Maker code
tCLS
CLE
tCLS
tCLH
tCS
CE
tWP
WE
tCH
tCSTO
tWHR
tCHZ*
RE
tDS
tDH
tIR
tRSTO
tRHZ*
Status Output
I/O
0
~
7
70h
tCLS
CLE
tCLS
tCLH
tCS
CE
tWP
WE
tCH
tCEA
tWHR
tCHZ*
RE
tDH
tDS
I/O
0
~
7
70h
tIR
tREA
tRHZ*
Status Output
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
2
K9F1208U0M-YCB0, K9F1208U0M-YIB0
FLASH MEMORY
Revision No
0.5
History
1. Addition of new operation : Multi-Plane Copy-Back Program.
- Multi-Plane Copy-Back Program is extended operation of one-page
Copy-Back program.
=> After successive reading of multiple 528 byte data set at the source
planes, the above data are moved to internal page registers and same
procedure as Multi-Plane Page Programming is executed.
1.Powerup sequence is added
: Recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences
~ 2.5V
Draft Date
May. 30th 2001
Remark
Preliminary
0.6
Jul. 23th 2001
≈
~ 2.5V
V
CC
High
WP
WE
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
0.7
1. Copy-Back Program(Dummy) is added in Command sets table.
(before revision)
Function
Page Program (True)
Page Program (Dummy)
Copy-Back Program(True)
1st.
Cycle
80h
80h
00h
2nd.
Cycle
10h
11h
8Ah
3rd.
Cycle
-
-
10h
≈
1µs
≈
Aug. 23th 2001
(after revision)
Function
Page Program (True)
(2)
Page Program (Dummy)
(2)
Copy-Back Program(True)
(2)
Copy-Back Program(Dummy)
(2)
1st.
Cycle
80h
80h
00h
03h
2nd.
Cycle
10h
11h
8Ah
8Ah
3rd.
Cycle
-
-
10h
11h/10h
Note 2. Page Program(True) and Copy-Back Program(True) are available on 1 plane
operation.
Page Program(Dummy) and Copy-Back Program(Dummy) are available on
the 2nd,3rd,4th plane of multi plane operation.
3
K9F1208U0M-YCB0, K9F1208U0M-YIB0
FLASH MEMORY
Revision No
0.8
History
1. In Read ID & Status Read timing diagram, tCLS is changed to tCLR.
CLE
CE
WE
tAR1
tCLS
tCEA
Draft Date
Oct. 7th 2001
Remark
ALE
RE
I/O
0
~
7
tWHR
tREA
90h
00h
Address. 1cycle
ECh
Maker code
CLE
CE
WE
tCLR
tCEA
tAR1
ALE
RE
I/O
0
~
7
tWHR
tREA
90h
00h
Address. 1cycle
ECh
Maker code
tCLS
CLE
tCLS
tCLH
tCS
CE
tWP
WE
tCH
tCEA
tWHR
tCHZ*
RE
tDH
tDS
I/O
0
~
7
70h
tIR
tREA
tRHZ*
Status Output
tCLR
CLE
tCLS
tCLH
tCS
CE
tWP
WE
tCH
tCEA
tWHR
tCHZ*
RE
tDH
tDS
I/O
0
~
7
70h
tIR
tREA
tRHZ*
Status Output
4
K9F1208U0M-YCB0, K9F1208U0M-YIB0
FLASH MEMORY
Revision No
0.9
History
To clarify the meaning of parameter,
1. tRHZ is devide into tRHZ and tOH.(page 12)
- tRHZ : RE High to Output Hi-Z
- tOH : RE High to Output Hold
2. tCHZ is devide into tCHZ and tOH.(page 12)
- tCHZ : CE High to Output Hi-Z
- tOH : CE High to Output Hold
Draft Date
Apr. 20th 2002
Remark
5
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