Fact Sheet
MPC7400FACT/D
Rev. 1
M
OTOROLA
MPC7400
P
OWER
PC
™
M
ICROPROCESSORS
The MPC7400 PowerPC microprocessor is a high-performance, low-power, 32-bit implementation of the PowerPC
Reduced Instruction Set Computer (RISC) architecture combined with a full 128-bit implementation of Motorola’s
AltiVec™ technology instruction set, creating a high-performance RISC microprocessor ideal for leading-edge
computing, control, and signal processing functions. The MPC7400 supports the high-bandwidth MPX bus with
minimized signal setup times and reduced idle cycles to increase maximum operating frequency to over 100 MHz,
increased address bus bandwidth, increased data bus bandwidth, and more enhancements. To maintain backward
compatibility for existing applications, the MPC7400 also supports the 60x bus protocol. MPC7400 microprocessors
offer single-cycle double-precision floating-point performance, provide full symmetric multiprocessing (SMP)
capabilities, and support up to 2MB of backside L2 cache. While the
MPC7400 Microprocessor
MPC7400 is software-compatible with existing applications for
PowerPC 603e™, PowerPC 740™, and PowerPC 750™
microprocessors, to utilize the full potential of this AltiVec
technology-enabled device, some instruction changes in existing source
code are required to interface with the vector execution unit.
Superscalar Microprocessor
MPC7400 microprocessors feature a high-frequency superscalar
PowerPC core, capable of issuing three instructions per clock cycle
(two instructions + branch) into seven independent execution units:
I
Two integer units
I
Double-precision floating-point unit
I
Vector unit
I
Load/store unit
Motorola MPC7400 Block Diagram
I
System unit
I
Branch processing unit
Completion
Branch
Unit
AltiVec Technology
Dispatch
Unit
Unit
Motorola’s AltiVec technology expands the capabilities of
Integer
Floating
Vector
PowerPC microprocessors by providing leading-edge,
Unit
Point Unit
Unit
general-purpose processing performance while
Integer
Floating Point
Vector
Reg File
Reg File
Reg File
concurrently addressing high-bandwidth data processing
and algorithmic-intensive computations in a single-chip
solution. AltiVec technology:
Load/Store Unit
I
Meets the computational demands of networking
D MMU
I MMU
infrastructure such as multichannel modems, echo
Data Cache
Instruction Cache
cancellation equipment, and basestation processing.
L2 Tags
Bus Interface Unit
I
Enables faster, more secure encryption methods
optimized for the SIMD processing model
64b L2
32b Address
64b Data
I
Cache Port
Provides compelling performance for multimedia-
oriented desktop computers, desktop publishing, and
60x/MPX Bus
FSRAM
digital video processing
I
Enables real-time processing of the most demanding
data streams (MPEG-2 encode, continuous speech recognition, real-time high-resolution 3D graphics, etc.)
Power Management
MPC7400 microprocessors feature a low-power 1.8-volt design with three power-saving user-programmable modes —
nap, doze (with bus snoop) and sleep— which progressively reduce the power drawn by the processor. The MPC7400
also provides a thermal assist unit and instruction cache throttling for software-controllable thermal management.
Cache and MMU Support
The MPC7400 microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches. Both caches
feature cache locking and are eight-way set-associative. The MPC7400 microprocessor’s dedicated L2 cache interface
with on-chip L2 tags features a very fast (up to core speed, 1:1) interface to memory, instruction-only or data-only
modes, and parity checking on both L2 address and data.
MPC7400 microprocessors contain separate memory management units (MMUs) for instructions and data, supporting
4 Petabytes (2
52
) of virtual memory and 4 Gigabytes (2
32
) of physical memory. They also offer four instruction block
address translation (iBAT) and four data block address translation (dBAT) registers.
MPX Bus Interface
MPC7400 microprocessors support the MPX bus architecture with a 64-bit data bus and a 32-bit address bus. Support
is included for burst, split and pipelined transactions, data streaming, out-of-order transactions, and data intervention (in
SMP systems). The interface provides snooping for
Motorola MPC7400 Processor Summary
data cache coherency. The MPC7400 implements
MPC7400
MERSI coherency protocol for multiprocessing in
350-500 MHz
hardware, allowing access to system memory for
350, 400, 450, and 500 MHz
CPU Speeds – Internal
additional caching bus masters, such as DMA
x3, x3.5, x4, x4.5, x5, x5.5,
CPU Bus Dividers
x6, x6.5, x7 x7.5, x8, x9
,
devices.
Bus Interface
64-bit
MPX/60x
3 (2 + Branch)
32-Kbyte instruction
32-Kbyte data
512 Kbyte,
1 Mbyte, or 2 Mbyte
1:1, 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1
5.0W/11.5W @ 400 MHz
83 mm
2
360 CBGA
0. 8µ 5LM CMOS
1
1.8V internal, 1.8/2.5/3.3V I/O
21.4 @ 450 MHz
20.4 @ 450 MHz
825 MIPS @ 450 MHz
Integer(2), Floating-Point, Vector,
Branch, Load/Store, System
Example Applications
I
Bus Protocol
Instructions per Clock
L1 Cache
L2 Cache
Core-to-L2 Frequency
Typical/Maximum
Power Dissipation
Die Size
Package
Process
Voltage
SPECint95 (estimated)
SPECfp95 (estimated)
Other Performance
Execution Units
I
I
Networking and telecommunications
infrastructure
High-performance computing (scientific,
medical, etc.)
Desktop and portable computing
Contact Information
Motorola offers user’s manuals, application notes,
sample code and full local support for the PowerPC
product line. For more information, visit:
http://motorola.com/PowerPC/
and
http://motorola.com/AltiVec/
For all other inquiries about Motorola products,
please contact the
Motorola Customer Response
Center
at:
1-800-521-6274
or
http://motorola.com/semiconductors
Motorola PowerPC 7xxx Part Number Key
XPC
7400
7xxx Series Device
(7400)
RX
400
Frequency
3 digits
L
K
Revision
Product Code
PPC Sample
XPC XC qualified
MPC Qualified
Package
RX CBGA w/o Lid
Spec Definition
L 1.8V, 105°C
P 2. 5V, 65°C
1
© 2000 Motorola, Inc. All rights reserved. Printed in the U.S.A. Motorola and the Motorola logo are registered trademarks and DigitalDNA, the DigitalDNA logo and AltiVec are
trademarks of Motorola, Inc. PowerPC, the PowerPC logo, PowerPC 603e, PowerPC 740, and PowerPC 750 are trademarks of International Business Machines Corporation and
used under license therefrom. All other trademarks are the property of their respective owners.
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