ASM3I623S00KF-16-SR datasheet, PDF

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ASM3I623S00KF-16-SR: DescriptionTiming-Safeâ¢ Peak EMI reduction IC; Categorylogic logic; File Size630KB，18 Pages; ManufacturerPulseCore Semiconductor Corporation

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ASM3I623S00KF-16-SR Overview

Timing-Safeâ¢ Peak EMI reduction IC

ASM3I623S00KF-16-SR Parametric

Parameter Name	Attribute value
Maker	PulseCore Semiconductor Corporation
package instruction	0.150 INCH, ROHS COMPLIANT, SOIC-16
Reach Compliance Code	unknow
series	3I
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G16
length	9.905 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	8
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
propagation delay (tpd)	0.35 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	3.9 mm
minfmax	50 MHz

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May 2007

rev 0.4

ASM3P623S00B/C/J/E/F/K

Timing-Safe™ Peak EMI reduction IC

General Features

•

Clock distribution with Timing-Safe™ Peak EMI

Reduction

Input frequency range: 20MHz - 50MHz

Zero input - output propagation delay

Low-skew outputs

•

Output-output skew less than 250pS

Device-device skew less than 700pS

ASM3P623S00B/C/J is the eight-pin version and accepts

one reference input and drives out one low-skew clock.

All parts have on-chip PLLs that lock to an input clock on

the CLKIN pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad, internal to the device.

Multiple ASM3P623S00E/F/K devices can accept the same

input clock and distribute it. In this case, the skew between

the outputs of the two devices is guaranteed to be less than

700pS.

All outputs have less than 200pS of cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than 250pS, and the output-to-output skew is

guaranteed to be less than 250pS.

Refer

“

Spread Spectrum Control and Input-Output Skew

Less than 200pS cycle-to-cycle jitter

Available in 16pin, 150mil SOIC, 4.4mm TSSOP

(ASM3P623S00/E/F/K), and in 8pin, 150 mil

SOIC, 4.4mm TSSOP Packages

(ASM3P623S00B/C/J)

•

3.3V operation

Industrial temperature range

Advanced CMOS technology

The First True Drop-in Solution

Functional Description

ASM3P623S00B/C/J/E/F/K is a versatile, 3.3V zero-delay

buffer designed to distribute high-speed Timing-Safe™

clocks with Peak EMI reduction. ASM3P623S00E/F/K

accepts one reference input and drives out eight low-skew

clocks.

available

16pin

Table”

for

deviations

and

Input-Output

Skew for

ASM3P623S00B/C/J and the ASM3P623S00E/F/K devices

The ASM3P623S00B/C/J and the ASM3P623S00E/F/K are

available in two different packages, as shown in the

ordering information table.

package.

SSON

The

SS%

Block Diagram

Modulation

XIN/CLKIN

XOUT

Crystal

Oscillator

Reference

Divider

Feedback

Divider

Phase

Detector

Loop

Filter

VCO

PLL

Feedforward

Divider

CLKOUT

GND

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008

•

Tel: 408-879-9077

•

Fax: 408-879-9018

www.pulsecoresemi.com

Notice: The information in this document is subject to change without notice.

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