BUK95/9629-100B
TrenchMOS™ logic level FET
Rev. 01 — 18 April 2003
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using
Philips High-Performance Automotive (HPA) TrenchMOS™ technology.
Product availability:
BUK9529-100B in SOT78 (TO-220AB)
BUK9629-100B in SOT404 (D
2
-PAK).
1.2 Features
s
Very low on-state resistance
s
175
°C
rated
s
Q101 compliant
s
Logic level compatible.
1.3 Applications
s
Automotive systems
s
Motors, lamps and solenoids
s
12 V, 24 V and 42 V loads
s
General purpose power switching.
1.4 Quick reference data
s
E
DS(AL)S
≤
152 mJ
s
I
D
≤
46 A
s
R
DSon
= 24 mΩ (typ)
s
P
tot
≤
157 W.
2. Pinning information
Table 1:
Pin
1
2
3
mb
Pinning - SOT78 and SOT404, simplified outline and symbol
Description
gate (g)
drain (d)
source (s)
mounting base;
connected to
drain (d)
2
MBK106
Simplified outline
mb
Symbol
mb
[1]
d
g
s
MBB076
1 2 3
1
3
MBK116
SOT78 (TO-220AB)
[1]
It is not possible to make connection to pin 2 of the SOT404 package.
SOT404 (D
2
-PAK)
Philips Semiconductors
BUK95/9629-100B
TrenchMOS™ logic level FET
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
T
mb
= 25
°C;
V
GS
= 5 V;
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 5 V;
Figure 2
I
DM
P
tot
T
stg
T
j
I
DR
I
DRM
peak drain current
total power dissipation
storage temperature
junction temperature
reverse drain current (DC)
peak reverse drain current
T
mb
= 25
°C
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
unclamped inductive load; I
D
= 46 A;
V
DS
≤
100 V; V
GS
= 5 V; R
GS
= 50
Ω;
starting T
mb
= 25
°C
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
mb
= 25
°C;
Figure 1
R
GS
= 20 kΩ
Conditions
Min
-
-
-
-
-
-
-
−55
−55
-
-
-
Max
100
100
±15
46
32
186
157
+175
+175
46
186
152
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source avalanche
energy
9397 750 11249
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 — 18 April 2003
2 of 15
Philips Semiconductors
BUK95/9629-100B
TrenchMOS™ logic level FET
120
Pder
(%)
80
03na19
60
ID
(A)
40
03nm56
40
20
0
0
50
100
150
200
Tmb
(°C)
0
0
50
100
150
200
Tmb (
°
C)
P
der
P
tot
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
V
GS
≥
5 V
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Continuous drain current as a function of
mounting base temperature.
103
03nm54
ID
(A)
Limit R DSon = VDS / ID
102
tp = 10
µ
s
100
µ
s
10
DC
1 ms
10 ms
100 ms
1
1
10
102
VDS (V)
103
T
mb
= 25
°C;
I
DM
single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 11249
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 — 18 April 2003
3 of 15
Philips Semiconductors
BUK95/9629-100B
TrenchMOS™ logic level FET
4. Thermal characteristics
Table 3:
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Conditions
Figure 4
Min Typ Max Unit
-
-
0.95 K/W
thermal resistance from junction to mounting
base
thermal resistance from junction to ambient
SOT78 (TO-220AB)
SOT404 (D
2
-PAK)
vertical in still air
minimum footprint; mounted on a PCB
-
-
60
50
-
-
K/W
K/W
Symbol Parameter
4.1 Transient thermal impedance
1
Zth(j-mb)
(K/W)
δ
= 0.5
0.2
0.1
0.05
0.02
03nm55
10-1
10-2
single shot
P
δ
=
tp
T
tp
T
10-3
10-6
10-5
10-4
10-3
10-2
10-1
t
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 11249
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 — 18 April 2003
4 of 15
Philips Semiconductors
BUK95/9629-100B
TrenchMOS™ logic level FET
5. Characteristics
Table 4:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol
V
(BR)DSS
Parameter
drain-source breakdown
voltage
Conditions
I
D
= 0.25 mA; V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
°C
T
j
= 175
°C
T
j
=
−55 °C
I
DSS
drain-source leakage current
V
DS
= 100 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 175
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state
resistance
V
GS
=
±15
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 175
°C
V
GS
= 4.5 V; I
D
= 25 A
V
GS
= 10 V; I
D
= 25 A
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
L
d
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain inductance
from drain lead 6 mm from
package to centre of die
from contact screw on
mounting base to centre of
die SOT78
from upper edge of drain
mounting base to centre of
die SOT404
L
s
internal source inductance
from source lead 6 mm from
package to source bond pad
V
DD
= 30 V; R
L
= 1.2
Ω;
V
GS
= 5 V; R
G
= 10
Ω
V
GS
= 0 V; V
DS
= 25 V;
f = 1 MHz;
Figure 12
V
GS
= 5 V; V
DD
= 80 V;
I
D
= 25 A;
Figure 14
-
-
-
-
-
-
-
-
-
-
-
-
33
7
13
3270
236
103
30
86
96
46
4.5
3.5
-
-
-
4360
283
141
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
nH
nH
-
-
-
-
24
-
-
22
29
75
32
27
mΩ
mΩ
mΩ
mΩ
-
-
-
0.02
-
2
1
500
100
µA
µA
nA
1.1
0.5
-
1.5
-
-
2
-
2.3
V
V
V
100
89
-
-
-
-
V
V
Min
Typ
Max
Unit
Static characteristics
-
2.5
-
nH
-
7.5
-
nH
9397 750 11249
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 — 18 April 2003
5 of 15
PCB Design
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