3.3 V, ±15 kV ESD-Protected, Half- and
Full-Duplex, RS-485/RS-422 Transceivers
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
FEATURES
TIA/EIA RS-485/RS-422 compliant
±15 kV ESD protection on RS-485 input/output pins
Data rates
ADM3070E/ADM3071E/ADM3072E: 250 kbps
ADM3073E/ADM3074E/ADM3075E: 500 kbps
ADM3076E/ADM3077E/ADM3078E: 16 Mbps
Half- and full-duplex options
True fail-safe receiver inputs
Up to 256 nodes on the bus
−40°C to +125°C temperature option
Hot-swap input structure on DE and RE pins
Reduced slew rates for low EMI
Low power shutdown current (all except ADM3071E/
ADM3074E/ADM3077E)
Outputs high-Z when disabled or powered off
Common-mode input range: −7 V to +12 V
Thermal shutdown and short-circuit protection
8-lead and 14-lead narrow SOIC packages
FUNCTIONAL BLOCK DIAGRAMS
V
CC
ADM3070E/
ADM3073E/
ADM3076E
RO
RE
DE
DI
D
Z
Y
06285-001
R
A
B
GND
Figure 1.
V
CC
ADM3071E/
ADM3074E/
ADM3077E
RO
R
A
B
APPLICATIONS
Power/energy metering
Industrial control
Lighting systems
Telecommunications
Security systems
Instrumentation
DI
D
Z
Y
06285-002
GND
Figure 2.
V
CC
GENERAL DESCRIPTION
The ADM307xE are 3.3 V, low power data transceivers with
±15 kV ESD protection suitable for full- and half-duplex
communication on multipoint bus transmission lines. They
are designed for balanced data transmission, and they comply
with TIA/EIA standards: RS-485 and RS-422.
The devices have a ⅛ unit load receiver input impedance, which
allows up to 256 transceivers on a bus. Because only one driver
should be enabled at any time, the output of a disabled or powered-
down driver is tristated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which eliminates
the need for external bias resistors and ensures a logic high
output level when the inputs are open or shorted. This guar-
antees that the receiver outputs are in a known state before
communication begins and when communication ceases.
RO
RE
DE
DI
ADM3072E/
ADM3075E/
ADM3078E
R
A
B
D
06285-003
GND
Figure 3.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2009 Analog Devices, Inc. All rights reserved.
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Timing Specifications—
ADM3070E/ADM3071E/ADM3072E....................................... 5
Timing Specifications—
ADM3073E/ADM3074E/ADM3075E....................................... 6
Timing Specifications—
ADM3076E/ADM3077E/ADM3078E....................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Test Circuits and Switching Characteristics ................................ 10
Typical Performance Characteristics ........................................... 12
Circuit Description......................................................................... 15
Function Tables........................................................................... 15
Receiver Fail-Safe ....................................................................... 15
Hot-Swap Capability .................................................................. 16
Line Length vs. Data Rate ......................................................... 16
±15 kV ESD Protection ............................................................. 16
Human Body Model .................................................................. 16
256 Transceivers on the Bus ...................................................... 16
Reduced EMI and Reflections .................................................. 16
Low Power Shutdown Mode ..................................................... 17
Driver Output Protection .......................................................... 17
Typical Applications ................................................................... 17
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
8/09—Rev. D to Rev. E
Changes to Ordering Guide .......................................................... 20
4/09—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 20
1/09—Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 20
8/08—Rev. A to Rev. B
Changes to Table 3 ............................................................................ 5
Changes to Figure 36 ...................................................................... 18
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
10/06—Rev. 0 to Rev. A
Added ADM3077E and ADM3078E ............................... Universal
Changes to Figure 2 and Figure 3 ................................................... 1
Changes to Figure 5 and Figure 6 ................................................... 9
Changes to Figure 34 and Figure 35 ............................................. 17
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
8/06—Revision 0: Initial Version
Rev. E | Page 2 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
The driver outputs of the 250 kbps and 500 kbps devices are slew
rate limited to reduce EMI and data errors caused by reflections
from improperly terminated buses. Excessive power dissipation
caused by bus contention or by output shorting is prevented
with a thermal shutdown circuit.
The parts are fully specified over the industrial temperature
ranges and are available in 8-lead and 14-lead narrow SOIC
packages.
Table 1. Selection Table
Part No.
ADM3070E
ADM3071E
ADM3072E
ADM3073E
ADM3074E
ADM3075E
ADM3076E
ADM3077E
ADM3078E
Half/Full
Duplex
Full
Full
Half
Full
Full
Half
Full
Full
Half
Data Rate
(Mbps)
0.25
0.25
0.25
0.5
0.5
0.5
16
16
16
Slew Rate
Limited
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Driver/Receiver
Enable
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Low Power
Shutdown
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Nodes on
Bus
256
256
256
256
256
256
256
256
256
±15 kV ESD
on Bus Pins
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Pin
Count
14
8
8
14
8
8
14
8
8
Rev. E | Page 3 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
SPECIFICATIONS
V
CC
= 3.3 V ± 10%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2. ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
Parameter
DRIVER
Differential Outputs
Differential Output Voltage
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
V
OD
2.0
1.5
Δ|V
OD
| for Complementary Output States
1
Common-Mode Output Voltage
Δ|V
OC
| for Complementary Output States
1
Short-Circuit Output Current
Short-Circuit Foldback Output Current
Output Leakage (Y, Z) Full Duplex
Logic Inputs
Input High Voltage
Input Low Voltage
Input Hysteresis
Logic Input Current
Input Impedance First Transition
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Input Hysteresis
Input Resistance (A, B)
Input Current (A, B)
RO Logic Output
Output High Voltage
Output Low Voltage
Short-Circuit Output Current
Tristate Output Leakage Current
POWER SUPPLY
Supply Current
ΔV
OD
V
OC
ΔV
OC
I
OSD
I
OSDF
I
O
V
CC
/2
40
−250
20
V
CC
V
CC
V
CC
0.2
3
0.2
250
−40
−20
125
−100
V
IH
V
IL
V
HYS
I
IN
T
TS
T
TSH
2.0
0.8
100
1
175
15
±1
10
V
V
V
V
V
V
mA
mA
mA
mA
μA
μA
V
V
mV
μA
kΩ
°C
°C
R
L
= 100 Ω (RS-422) (see Figure 7)
R
L
= 54 Ω (RS-485) (see Figure 7)
No load
R
L
= 54 Ω or 100 Ω (see Figure 7)
R
L
= 54 Ω or 100 Ω (see Figure 7)
R
L
= 54 Ω or 100 Ω (see Figure 7)
0 V < V
OUT
< 12 V
−7 V < V
OUT
< V
CC
(V
CC
− 1 V) < V
OUT
< 12 V
−7 V < V
OUT
< +1 V
DE = 0 V, RE = 0 V, V
CC
= 0 V or 3.6 V, V
IN
= 12 V
DE = 0 V, RE = 0 V, V
CC
= 0 V or 3.6 V, V
IN
= −7 V
DE, DI, RE
DE, DI, RE
DE, DI, RE
DE, DI, RE
DE
V
TH
ΔV
TH
R
IN
I
A,
I
B
−200
96
−125
15
−50
125
−100
mV
mV
kΩ
μA
μA
V
V
mA
μA
mA
mA
mA
μA
kV
kV
−7 V < V
CM
< +12 V
V
A
+ V
B
= 0 V
−7 V < V
CM
< +12 V
DE = 0 V, V
CC
= 0 V or 3.6 V, V
IN
= 12 V
DE = 0 V, V
CC
= 0 V or 3.6 V, V
IN
= −7 V
I
OUT
= −1 mA
I
OUT
= 1 mA
0 V < V
RO
< V
CC
V
CC
= 3.6 V, 0 V < V
OUT
< V
CC
No load, DE = V
CC
, RE = 0 V
No load, DE = V
CC
, RE = V
CC
No load, DE = 0 V, RE = 0 V
DE = 0 V, RE = V
CC
Human body model
Human body model
V
OH
V
OL
I
OSR
I
OZR
I
CC
V
CC
− 0.6
0.4
±80
±1
0.8
0.8
0.8
0.05
±15
±4
1.5
1.5
1.5
10
Shutdown Current
ESD PROTECTION
A, B, Y, Z Pins
All Pins Except A, B, Y, Z Pins
1
I
SHDN
Δ|V
OD
| and Δ|V
OC
| are the changes in V
OD
and V
OC
, respectively, when the DI input changes state.
Rev. E | Page 4 of 20
ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E
TIMING SPECIFICATIONS—ADM3070E/ADM3071E/ADM3072E
V
CC
= 3.3 V ± 10%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay, Low-to-High Level
Propagation Delay, High-to-Low Level
Rise Time/Fall Time
|t
DPLH
− t
DPHL
| Differential Driver Output Skew
Enable to Output High
Enable to Output Low
Disable Time from Low
Disable Time from High
Enable Time from Shutdown to High
Enable Time from Shutdown to Low
RECEIVER
Maximum Data Rate
Propagation Delay, Low-to-High Level
Propagation Delay, High-to-Low Level
|t
RPLH
− t
RPHL
| Output Skew
Enable to Output High
Enable to Output Low
Disable Time from Low
Disable Time from High
Enable Time from Shutdown to High
Enable Time from Shutdown to Low
TIME TO SHUTDOWN
1
Symbol
Min
250
250
250
350
Typ
Max
Unit
kbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
t
DPLH
t
DPHL
t
DR
/t
DF
t
DSKEW
t
DZH
t
DZL
t
DLZ
t
DHZ
t
DZH(SHDN)
t
DZL(SHDN)
1500
1500
1600
200
2500
2500
100
100
5500
5500
C
L
= 50 pF, R
L
= 54 Ω (see Figure 8 and Figure 9)
C
L
= 50 pF, R
L
= 54 Ω (see Figure 8 and Figure 9)
C
L
= 50 pF, R
L
= 54 Ω (see Figure 8 and Figure 9)
C
L
= 50 pF, R
L
= 54 Ω (see Figure 8 and Figure 9)
1
See Figure 10
See Figure 11
See Figure 11
See Figure 10
See Figure 10
See Figure 11
250
t
RPLH
t
RPHL
t
RSKEW
t
RZH
t
RZL
t
RLZ
t
RHZ
t
RZH(SHDN)
t
RZL(SHDN)
t
SHDN
200
200
30
50
50
50
50
4000
4000
600
C
L
= 15 pF (see Figure 12 and Figure 13)
C
L
= 15 pF (see Figure 12 and Figure 13)
C
L
= 15 pF (see Figure 12 and Figure 13)
See Figure 14
See Figure 14
See Figure 14
See Figure 14
See Figure 14
See Figure 14
50
200
V
CC
= 3.3 V.
Rev. E | Page 5 of 20
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