Features
•
E
2
Programmable 524,288 x 1 and 1,048,576 x 1 bit Serial Memories Designed To Store
•
•
•
•
•
•
•
•
•
•
Configuration Programs For Field Programmable Gate Arrays (FPGA)
Simple Interface to SRAM FPGAs
Compatible With Atmel AT6000, AT40K FPGAs, Altera EPF8K, EPF10K,
EPF6K FPGAs, ORCA FPGAs, Xilinx XC3000, XC4000, XC5200 FPGAs, Motorola
MPA1000 FPGAs
Cascadable To Support Additional Configurations or Future Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available In PLCC Package (Pin Compatable across Product Family)
In-System Programmable Via 2-Wire Bus
Emulation of 24CXX Serial EPROMs
Available in 3.3V
±
10% LV and 5V Versions
System Friendly READY Pin
Description
The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configu-
ration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration
memory for Field Programmable Gate Arrays. The high-density AT17 Series is pack-
aged in the popular 20-pin PLCC. The high-density AT17 Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The high-density
AT17 Series organization supplies enough memory to configure one or multiple
smaller FPGAs. The user can select the polarity of the reset function by programming
one EEPROM byte. The devices also support a write protection mode and a system
friendly READY pin, which signifies a “good” power level to the device and can be
used to ensure reliable system power-up.
The high-density AT17 Series can be programmed with industry-standard program-
mers, and the Atmel ATDH2200 Programming board.
FPGA
Configuration
E
2
PROM
Memory
512K and 1M
AT17C512
AT17LV512
AT17C010
AT17LV010
Pin Configurations
20-Pin PLCC
N
C
D
A
T
A
N
C
V
C
C
N
C
3
CLK
WP1
RESET/OE
WP2
CE
2
1
20
4
5
6
7
8
9
N
C
19
18
17
16
15
14
13
N
C
NC
SER_EN
NC
R E A DY
CEO
10
G
N
D
11
N
C
12
N
C
Rev. 0944A-A–12/97
1
Controlling The High-Density AT17 Series Serial EEPROMs
Most connections between the FPGA device and the Serial
EEPROM are simple and self-explanatory:
• The DATA output of the high-density AT17 Series drives
DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of
the high-density AT17 Series.
• The CEO output of any AT17C/LV512/010 drives the CE
input of the next AT17C/LV512/010 in a cascade chain of
PROMs.
• SER_EN must be connected to V
CC
, (except during
ISP).
READY is available as an open-collector indicator of the
device’s RESET status; it is driven Low while the device is
in its POWER-ON RESET cycle and released (tri-stated)
when the cycle is complete.
There are two different ways to use the inputs CE and OE,
as shown in the AC Characteristics waveforms.
its simplicity, however, this method will fail if the FPGA
receives an external reset condition during the configura-
tion cycle. If a system reset is applied to the FPGA, it will
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the high-density
AT17 Series does not see the external reset signal and will
not reset its internal address counters and, consequently,
will remain out of sync with the FPGA for the remainder of
the configuration cycle.
Condition 2
The FPGA D/P output drives only the CE input of the high-
density AT17 Series, while its OE input is driven by the
inversion of the input to the FPGA RESET input pin. This
connection works under all normal circumstances, even
when the user aborts a configuration before D/P has gone
High. A High lev el on the RES ET/OE inpu t to the
AT17C/LVxxx – during FPGA reset – clears the Configura-
tor’s internal address pointer, so that the reconfiguration
starts at the beginning. The high-density AT17 Series does
not require an inverter since the RESET polarity is pro-
grammable.
Condition 1
The simplest connection is to have the FPGA D/P output
drive both CE and RESET/OE in parallel (Figure 1). Due to
Block Diagram
2
AT17C/LV512/010
AT17C/LV512/010
Pin Configurations
20
PLCC
2
4
5
6
Name
DATA
CLK
WP1
RESET/OE
I/O
I/O
I
I
I
Description
Three-state DATA output for reading. Input/Output pin for programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WRITE PROTECT (1). Used to protect portions of memory during programming. See
programming guide for details.
RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and
RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the
address and bit counters. The logic polarity of this input is programmable as either RESET/OE
or RESET/OE. This document describes the pin as RESET/OE.
WRITE PROTECT (2). Used to protect portions of memory during programming. See
programming guide for details.
Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data
output driver. A High level on CE disables both the address and bit counters and forces the
device into a low power mode. Note this pin will not enable/disable the device in 2-wire Serial
Programming mode (i.e., when SER_EN is Low).
Ground pin.
O
Chip Enable Out output. This signal is asserted Low on the clock cycle following the last bit
read from the memory. It will stay Low as long as CE and OE are both Low. It will then follow
CE until OE goes High. Thereafter, CEO will stay High until the entire PROM is read again and
senses the status of RESET polarity.
Device selection input, A2. This is used to enable (or select) the device during programming,
when SER_EN is Low (see Programming Guide for more details)
Open collector reset state indicator. Driven Low during power-up reset, released when power-
up is complete. (Recommend a 4.7KΩ Pull-up on this pin if used).
Serial enable is normally high during FPGA loading operations. Bringing SER_EN Low,
enables the two wire serial interface mode for programming.
+3.3V/+5V power supply pin.
7
8
WP2
CE
I
I
10
14
GND
CEO
A2
15
17
20
READY
SER_EN
V
CC
I
O
I
Absolute Maximum Ratings*
Operating Temperature .................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground ............................ -0.1V to V
CC
+ 0.5V
Supply Voltage (V
CC
) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 s @ 1/16 in.)..................260°C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100 pF)............................... 2000V
*NOTICE:
Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Rat-
ings conditions for extended periods of time may
affect device reliability.
3
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associ-
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power up, or on command, depending on the state of the
three FPGA mode pins. In Master Mode, the FPGA auto-
matically loads the configuration program from an external
memory. The Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
After configuration is complete, the address counters of all
cascaded Configurators are reset if the reset signal drives
the RESET/OE on each Configurator to its active (High)
level.
If the address counters are not to be reset upon comple-
tion, then the RESET/OE inputs can be tied to ground. For
more details, please reference the AT17C Series Program-
ming Guide.
Programming Mode
Cascading Serial Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded Configurators provide additional memory.
As the last bit from the first Configurator is read, the clock
signal to the Configurator asserts its CEO output Low and
disables its DATA line. The second Configurator recog-
nizes the Low level on its CE input and enables its DATA
output.
Figure 1.
Condition 1 Connection
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the 2-
wire interface. The programming is done at V
CC
supply
only. Programming super voltages are generated inside the
chip. See the Programming Specification for Atmel's Con-
figuration Memories Application Note for further informa-
tion. The AT17C Series parts are read/write at 5V nominal.
The AT17LV parts are read/write at 3.3V nominal.
AT17C/LVXXX Reset Polarity
The AT17C/LVXXX lets the user choose the reset polarity
as either RESET/OE or RESET/OE.
Standby Mode
The AT17C/LVXXX enters a low-power standby mode
whenever CE is asserted High. In this mode, the Configura-
tor consumes less than 0.5mA at 5.0 volts. The output
remains in a high impedance state regardless of the state
of the OE input.
Operating Conditions
AT17CXXX
Symbol
Description
Commercial
V
CC
Industrial
Military
Supply voltage relative to GND
-0°C to +70°C
Supply voltage relative to GND
-40°C to +85°C
Supply voltage relative to GND
-55°C to +125°C
Min/Max
4.75 / 5.25
4.5 / 5.5
4.5 / 5.5
AT17LVXXX
Min/Max
3.0 / 3.6
3.0 / 3.6
3.0 / 3.6
Units
V
V
V
4
AT17C/LV512/010
AT17C/LV512/010
DC Characteristics
V
CC
= 5V
±
5% Commercial / 5V
±
10% Ind./Mil.
Symbol
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
I
CCA
I
L
I
CCS
Description
High-level input voltage
Low-level input voltage
High-level output voltage (I
OH
= -4 mA)
Low-level output voltage (I
OL
= +4 mA)
High-level output voltage (I
OH
= -4 mA)
Low-level output voltage (I
OL
= +4 mA)
High-level output voltage (I
OH
= -4 mA)
Low-level output voltage (I
OL
= +4 mA)
Supply current, active mode (at FMAX)
Input or output leakage current (V
IN
= V
CC
or GND)
Commercial
Supply current, standby mode
Industrial/Military
0.5
mA
-10
3.7
Military
0.4
10
10
0.5
V
mA
µA
mA
3.76
Industrial
0.37
V
V
Commercial
0.32
V
V
Min
2.0
0
3.86
Max
V
CC
0.8
Units
V
V
V
DC Characteristics
V
CC
= 3.3V
±
10%
Symbol
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
I
CCA
I
L
I
CCS
Description
High-level input voltage
Low-level input voltage
High-level output voltage (I
OH
= -2.5 mA)
Low-level output voltage (I
OL
= +3 mA)
High-level output voltage (I
OH
= -2 mA)
Low-level output voltage (I
OL
= +3 mA)
High-level output voltage (I
OH
= -2 mA)
Low-level output voltage (I
OL
= +2.5 mA)
Supply current, active mode
Input or output leakage current (V
IN
= V
CC
or GND)
Commercial
Supply current, standby mode
Industrial/Military
100
-10
2.4
Military
0.4
5
10
100
V
mA
µA
µA
µA
2.4
Industrial
0.4
V
V
Commercial
0.4
V
V
Min
2.0
0
2.4
Max
V
CC
0.8
Units
V
V
V
5
京公网安备 11010802033920号
EEWORLD
