ZL30410
Multi-service Line Card PLL
Data Sheet
Features
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•
•
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Generates clocks for OC-3, STM-1, DS3, E3,
DS2, DS1, E1, 19.44 MHz and ST-BUS
Meets jitter generation requirements for STM-1,
OC-3, DS3, E3, J2 (DS2), E1 and DS1 interfaces
Compatible with GR-253-CORE SONET stratum
3 and G.813 SEC timing compliant clocks
Provides “hit-less” reference switching
Detects frequency of both reference clocks and
synchronizes to any combination of 8 kHz, 1.544
MHz, 2.048 MHz and 19.44 MHz reference
frequencies
Continuously monitors both references for
frequency accuracy exceeding ±12 ppm
Holdover accuracy of 70x10
-12
meets GR-1244
Stratum 3E and ITU-T G.812 requirements
Meets requirements of G.813 Option 1 for SDH
Equipment Clocks (SEC) and GR-1244 for
Stratum 4E and Stratum 4 Clocks
3.3V power supply
Ordering Information
ZL30410QCC
80 Pin LQFP
November 2003
-40°C to 85°C
•
Clock generation for ST-BUS and GCI timing
Description
The ZL30410 is a Multi-service Line Card
Phase-Locked Loop designed to generate multiple
clocks for SONET, SDH and PDH equipment including
timing for ST-BUS and GCI interfaces.
The ZL30410 operates in NORMAL (LOCKED),
HOLDOVER and FREE-RUN modes to ensure that in
the presence of jitter and interruptions to the reference
signals, the generated clocks meet international
standards. The filtering characteristics of the PLL are
hardware pin selectable and they do not require any
external adjustable components. The ZL30410 uses an
external 20 MHz Master Clock Oscillator to provide a
stable timing source for the HOLDOVER operation.
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Applications
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•
Line Card synchronization for SDH, SONET, DS3,
E3, J2 (DS2), E1 and DS1 interfaces
Timing card synchronization for SDH and PDH
Network Elements
VDD GND
C20i
FCS
OE
PRI
PRIOR
Primary
Acquisition
PLL
Master Clock
Frequency
Calibration
APLL
MUX
SEC
SECOR
RefSel
RESET
Core PLL
Clock
Synthesizer
Secondary
Acquisition
PLL
C155P/N
C34/C44
C19o
C16o
C8o
C6o
C4o
C2o
C1.5o
F16o
F8o
F0o
E3DS3/OC3
E3/DS3
Control State Machine
JTAG
IEEE
1149.1a
Tclk
Tdi
Tdo
Tms
Trst
07
MS1 MS2
RefAlign
LOCK
HOLDOVER
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30410
Table of Contents
Data Sheet
1.0 ZL30410 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Acquisition PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Core PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 Digitally Controlled Oscillator (DCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.2 Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.3 Lock Indicator (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.4 Reference Alignment (RefAlign). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Clock Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 Output Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Control State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1 Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.2 ZL30410 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.3 State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.0 Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 ZL30410 Switching Between Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1 System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . . . . . . 16
4.1.2 Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . 17
4.1.3 Single 8 kHz Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.4 Dual Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL. . . . . 19
4.1.5 Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . . . . . 20
4.2 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2
Zarlink Semiconductor Inc.
ZL30410
1.0
1.1
Data Sheet
ZL30410 Pinout
Pin Connections
IC
IC
NC
LOCK
NC
HOLDOVER
VDD
C34/C44
GND
C20i
NC
VDD
RefAlign
RefSel
C19o
GND
IC
C6o
C1.5o
PRIOR
60
62
38
64
36
66
34
68
32
70
72
28
74
26
76
24
78
22
80
2
4
6
8
10
12
14
16
18
20
58
56
54
52
50
48
46
44
42 40
SECOR
OE
NC
RESET
NC
IC
IC
IC
IC
GND
IC
IC
VDD
IC
IC
IC
IC
NC
NC
IC
ZL30410
30
NC
NC
Tdi
Trst
Tclk
Tms
Tdo
NC
GND
C155P
C155N
VDD
AVDD
GND
IC
GND
PRI
SEC
E3/DS3
E3DS3/OC3
Figure 2 - Pin Connections for 80-pin LQFP package
IC
NC
NC
NC
NC
GND
NC
NC
FCS
VDD
GND
F16o
C16o
C8o
C4o
C2o
F0o
MS1
MS2
F8o
3
Zarlink Semiconductor Inc.
ZL30410
Pin Description
Pin #
1
2-5
6
7, 8
9
Name
IC
NC
GND
NC
FCS
Description
Internal Connection.
Leave unconnected.
No internal bonding Connection.
Leave unconnected.
Ground.
Negative power supply.
No internal bonding Connection.
Leave unconnected.
Data Sheet
.
Filter Characteristic Select
(Input). In Hardware Control, FCS selects the
filtering characteristics of the ZL30410. Set this pin high to have a loop filter
corner frequency of 6 Hz and limit the phase slope to 41 ns per 1.326 ms. Set
this pin low to have corner frequency of 12 Hz with no phase slope limiting
imposed. This pin is internally pulled down to GND.
Positive Power Supply.
Ground.
Frame Pulse ST-BUS 8.192 Mb/s
(CMOS tristate output). This is an 8 kHz,
61ns wide, active low framing pulse, which marks beginning of a ST-BUS
frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mb/s.
Clock 16.384 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
Clock 8.192 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
Clock 4.096 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
Clock 2.048 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
Frame Pulse ST-BUS 2.048 Mb/s
(CMOS tristate output). This is an 8 kHz,
244ns, active low framing pulse, which marks the beginning of a ST-BUS
frame. This is typically used for ST-BUS operation at 2.048 Mb/s and 4.096
Mb/s.
Mode Select 1
(Input). The MS1 and MS2 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 14 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
Mode Select 2
(Input). The MS2 and MS1 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 14 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
Frame Pulse ST-BUS/GCI 8.192 Mb/s
(CMOS tristate output). This is an 8
kHz, 122 ns, active high framing pulse, which marks the beginning of a
ST-BUS/GCI frame. This is typically used for ST-BUS/GCI operation at 8.192
Mb/s. See Figure 15 for details.
10
11
12
VDD
GND
F16o
13
14
15
16
17
C16o
C8o
C4o
C2o
F0o
18
MS1
19
MS2
20
F8o
4
Zarlink Semiconductor Inc.
ZL30410
Pin Description (continued)
Pin #
21
Name
E3DS3/OC3
Description
Data Sheet
E3DS3 or OC3 Selection
(Input). In Hardware Control, a logic low on this pin
enables the C155P/N outputs (pin 30 and pin 31) and sets the C34/C44 output
(pin 53) to provide C8 or C11 clocks. Logic high at this input disables the C155
clock outputs (high impedance) and sets C34/C44 output to provide C34 and
C44 clocks.
E3 or DS3 Selection
(Input). In Hardware Control, when the E3DS3/OC3 pin
is set high, logic low on E3/DS3 pin selects a 44.736 MHz clock on C34/C44
output and logic high selects 34.368 MHz clock. When E3DS3/OC3 pin is set
low, logic low on E3/DS3 pin selects 11.184 MHz clock on C34/C44 output and
logic high selects 8.592 MHz clock.
Secondary Reference
(Input). This input is used as a secondary reference
source for synchronization. The ZL30410 can synchronize to the falling edge
of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44
MHz clock. In Hardware Control, selection of the input reference is based upon
the RefSel control input. This pin is internally pulled up to VDD.
Primary Reference
(Input). This input is used as a primary reference source
for synchronization. The ZL30410 can synchronize to the falling edge of the 8
kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz
clock. In Hardware Control, selection of the input reference is based upon the
RefSel control input. This pin is internally pulled up to VDD.
Ground.
Internal Connection.
Leave unconnected.
Ground.
Positive Analog Power Supply.
Connect this pin to VDD.
Positive Power Supply.
Clock 155.52MHz
(LVDS output). Differential outputs for the 155.52 MHz
clock. These outputs are enabled by applying logic low to E3DS3/OC3 input or
they can be disabled by applying logic high. In the disabled state the LVDS
outputs are internally terminated with an integrated 100Ω resistor (two 50Ω
resistors connected in series). The middle point of these resistors is internally
biased from a 1.25V LVDS bias source.
Ground.
No internal bonding Connection.
Leave unconnected.
IEEE1149.1a Test Data Output
(CMOS output). JTAG serial data is output on
this pin on the falling edge of Tclk clock. If not used, this pin should be left
unconnected.
IEEE1149.1a Test Mode Selection
(3.3 V input). JTAG signal that controls the
state transition on the TAP controller. This pin is internally pulled up to VDD. If
not used, this pin should be left unconnected.
22
E3/DS3
23
SEC
24
PRI
25
26
27
28
29
30
31
GND
IC
GND
AVDD
VDD
C155N
C155P
32
33
34
GND
NC
Tdo
35
Tms
5
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