PCA9534
8-bit I
2
C-bus and SMBus low power I/O port with interrupt
Rev. 03 — 6 November 2006
Product data sheet
1. General description
The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel
Input/Output (GPIO) expansion for I
2
C-bus/SMBus applications and was developed to
enhance the NXP Semiconductors family of I
2
C-bus I/O expanders. The improvements
include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a
simple solution when additional I/O is needed for ACPI power switches, sensors,
push buttons, LEDs, fans, etc.
The PCA9534 consists of an 8-bit Configuration register (Input or Output selection); 8-bit
Input register, 8-bit Output register and an 8-bit Polarity Inversion register (active HIGH or
active LOW operation). The system master can enable the I/Os as either inputs or outputs
by writing to the I/O configuration bits. The data for each input or output is kept in the
corresponding Input or Output register. The polarity of the Input Port register can be
inverted with the Polarity Inversion register. All registers can be read by the system
master. Although pin-to-pin and I
2
C-bus address compatible with the PCF8574 series,
software changes are required due to the enhancements and are discussed in
Application
Note AN469.
The PCA9534 is identical to the PCA9554 except for the removal of the internal I/O pull-up
resistor which greatly reduces power consumption when the I/Os are held LOW.
The PCA9534 open-drain interrupt output is activated when any input state differs from its
corresponding input port register state and is used to indicate to the system master that
an input state has changed. The power-on reset sets the registers to their default values
and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
2
C-bus address and allow up to eight
devices to share the same I
2
C-bus/SMBus.
2. Features
I
I
I
I
I
I
I
I
I
8-bit I
2
C-bus GPIO
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity Inversion register
Active LOW interrupt output
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
NXP Semiconductors
PCA9534
8-bit I
2
C-bus and SMBus low power I/O port with interrupt
I
8 I/O pins which default to 8 inputs
I
0 Hz to 400 kHz clock frequency
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Offered in four different packages: SO16, TSSOP16, and HVQFN16 (4
×
4
×
0.85 mm
and 3
×
3
×
0.85 mm versions)
3. Ordering information
Table 1.
Ordering information
T
amb
=
−
40
°
C to +85
°
C.
Type number
PCA9534D
PCA9534PW
PCA9534BS
PCA9534BS3
Topside
mark
PCA9534D
PCA9534
9534
P34
Package
Name
SO16
TSSOP16
HVQFN16
HVQFN16
Description
plastic small outline package; 16 leads; body width 7.5 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4
×
4
×
0.85 mm
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3
×
3
×
0.85 mm
Version
SOT162-1
SOT403-1
SOT629-1
SOT758-1
4. Block diagram
PCA9534
A0
A1
A2
8-bit
SCL
SDA
INPUT
FILTER
I
2
C-BUS/SMBus
CONTROL
write pulse
read pulse
POWER-ON
RESET
INPUT/
OUTPUT
PORTS
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V
DD
V
DD
V
SS
LP
FILTER
002aac469
INT
All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9534
PCA9534_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 6 November 2006
2 of 25
NXP Semiconductors
PCA9534
8-bit I
2
C-bus and SMBus low power I/O port with interrupt
5. Pinning information
5.1 Pinning
A0
A1
A2
IO0
IO1
IO2
IO3
V
SS
1
2
3
4
5
6
7
8
002aac465
16 V
DD
15 SDA
14 SCL
13 INT
12 IO7
11 IO6
10 IO5
9
IO4
A0
A1
A2
IO0
IO1
IO2
IO3
V
SS
1
2
3
4
5
6
7
8
002aac466
16 V
DD
15 SDA
14 SCL
13 INT
12 IO7
11 IO6
10 IO5
9
IO4
PCA9534D
PCA9534PW
Fig 2. Pin configuration for SO16
13 SDA
14 V
DD
16 A1
15 A0
terminal 1
index area
Fig 3. Pin configuration for TSSOP16
16 A1
15 A0
terminal 1
index area
13 SDA
12 SCL
11 INT
10 IO7
9
5
6
7
8
IO6
IO5
14 V
DD
IO4
A2
IO0
IO1
IO2
1
2
12 SCL
11 INT
A2
IO0
IO1
IO2
1
2
PCA9534BS
3
4
5
6
7
8
10 IO7
9
IO6
3
4
PCA9534BS3
V
SS
002aac467
V
SS
IO3
IO4
IO5
IO3
002aac468
Transparent top view
Transparent top view
Fig 4. Pin configuration for HVQFN16
(SOT629-1; 4
×
4
×
0.85 mm)
Fig 5. Pin configuration for HVQFN16
(SOT758-1; 3
×
3
×
0.85 mm)
5.2 Pin description
Table 2.
Symbol
A0
A1
A2
IO0
IO1
IO2
IO3
V
SS
IO4
IO5
PCA9534_3
Pin description
Pin
SO16, TSSOP16
1
2
3
4
5
6
7
8
9
10
HVQFN16
15
16
1
2
3
4
5
6
[1]
7
8
address input 0
address input 1
address input 2
input/output 0
input/output 1
input/output 2
input/output 3
ground supply voltage
input/output 4
input/output 5
© NXP B.V. 2006. All rights reserved.
Description
Product data sheet
Rev. 03 — 6 November 2006
3 of 25
NXP Semiconductors
PCA9534
8-bit I
2
C-bus and SMBus low power I/O port with interrupt
Pin description
…continued
Pin
SO16, TSSOP16
HVQFN16
9
10
11
12
13
14
input/output 6
input/output 7
interrupt output (open-drain)
serial clock line
serial data line
supply voltage
11
12
13
14
15
16
Description
Table 2.
Symbol
IO6
IO7
INT
SCL
SDA
V
DD
[1]
HVQFN package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must be
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level
performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the
board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in
the thermal pad region.
6. Functional description
Refer to
Figure 1 “Block diagram of PCA9534”.
6.1 Registers
6.1.1 Command byte
Table 3.
Command
0
1
2
3
Command byte
Protocol
read byte
read/write byte
read/write byte
read/write byte
Function
Input Port register
Output Port register
Polarity Inversion register
Configuration register
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
6.1.2 Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default ‘X’ is determined by the externally applied logic level.
PCA9534_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 6 November 2006
4 of 25
NXP Semiconductors
PCA9534
8-bit I
2
C-bus and SMBus low power I/O port with interrupt
Register 0 - Input Port register bit description
Symbol
I7
I6
I5
I4
I3
I2
I1
I0
Access
read only
read only
read only
read only
read only
read only
read only
read only
Value
X
X
X
X
X
X
X
X
Description
determined by externally applied logic level
Table 4.
Bit
7
6
5
4
3
2
1
0
6.1.3 Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.
Bit values in this register have no effect on pins defined as inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection,
not
the actual pin
value.
Table 5.
Register 1 - Output Port register bit description
Legend: * default value.
Bit
7
6
5
4
3
2
1
0
Symbol
O7
O6
O5
O4
O3
O2
O1
O0
Access
R
R
R
R
R
R
R
R
Value
1*
1*
1*
1*
1*
1*
1*
1*
Description
reflects outgoing logic levels of pins defined as
outputs by Register 3
6.1.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.
Table 6.
Register 2 - Polarity Inversion register bit description
Legend: * default value.
Bit
7
6
5
4
3
2
1
0
Symbol
N7
N6
N5
N4
N3
N2
N1
N0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0*
0*
0*
0*
0*
0*
0*
0*
Description
inverts polarity of Input Port register data
0 = Input Port register data retained (default value)
1 = Input Port register data inverted
PCA9534_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 6 November 2006
5 of 25
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