Features
•
Low-Voltage and Standard-Voltage Operation
– 5.0 (V
CC
= 4.5V to 5.5V)
– 2.7 (V
CC
= 2.7V to 5.5V)
– 2.5 (V
CC
= 2.5V to 5.5V)
– 1.8 (V
CC
= 1.8V to 5.5V)
Low-Power Devices (I
SB
= 2
µ
A @ 5.5V) Available
Internally Organized 4096 x 8, 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
Write Protect Pin for Hardware Data Protection
32-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >3,000V
Automotive Grade and Extended Temperature Devices Available
8-Pin JEDEC PDIP, 8-Pin and 14-Pin JEDEC SOIC, 8-Pin EIAJ SOIC,
and 8-pin TSSOP Packages
•
•
•
•
•
•
•
•
•
•
2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
•
•
Description
The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and pro-
grammable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2-
wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The AT24C32/64 is
available in space saving 8-pin JEDEC PDIP, 8-pin and 14-pin JEDEC SOIC, 8-pin
EIAJ SOIC, and 8-pin TSSOP packages and is accessed via a 2-wire serial interface.
In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V),
2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
8-Pin PDIP
AT24C32
AT24C64
Pin Configurations
Pin Name
A0 to A2
SDA
SCL
WP
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
2-Wire, 32K
Serial E
2
PROM
8-Pin TSSOP
14-Pin SOIC
NC
A0
A1
NC
A2
GND
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
VCC
WP
NC
SCL
SDA
NC
8-Pin SOIC
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Rev. 0336F–08/98
1
Absolute Maximum Ratings*
Operating Temperature .................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Block Diagram
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0):
The A2, A1
and A0 pins are device address inputs that are hard wired
or left not connected for hardware compatibility with
AT24C16. When the pins are hardwired, as many as eight
32K/64K devices may be addressed on a single bus sys-
tem (device addressing is discussed in detail under the
Device Addressing section). When the pins are not hard-
wired, the default A
2
, A
1
, and A
0
are zero.
WRITE PROTECT (WP):
The write protect input, when tied
to GND, allows normal write operations. When WP is tied
high to V
CC
, all write operations to the upper quandrant
(8/16K bits) of memory are inhibited. If left unconnected,
WP is internally pulled down to GND.
Memory Organization
AT24C32/64, 32K/64K SERIAL EEPROM:
The 32K/64K is
internally organized as 256 pages of 32 bytes each. Ran-
dom word addressing requires a 12/13 bit data word
address.
2
AT24C32/64
AT24C32/64
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +1.8V.
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
0
, A
1
, A
2
, SCL)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40°C to +85°C, V
CC
= +1.8V to +5.5V, T
AC
= 0°C to +70°C,
V
CC
= +1.8V to +5.5V (unless otherwise noted).
Symbol
V
CC1
V
CC2
V
CC3
V
CC4
I
CC1
I
CC2
I
SB1
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current V
CC
= 5.0V
Supply Current V
CC
= 5.0V
Standby Current
(1.8V option)
Standby Current
(2.5V option)
Standby Current
(2.7V option)
Standby Current
(5V option)
Input Leakage Current
Output Leakage Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level V
CC
= 3.0V
Output Low Level V
CC
= 1.8V
I
OL
= 2.1 mA
I
OL
= 0.15 mA
V
CC
= 1.8V
V
CC
= 5.5V
V
CC
= 2.5V
V
CC
= 5.5V
V
CC
= 2.7V
V
CC
= 5.5V
V
CC
= 4.5 - 5.5V
READ at 100 kHz
WRITE at 100 kHz
V
IN
= V
CC
or V
SS
Test Condition
Min
1.8
2.5
2.7
4.5
0.4
2.0
Typ
Max
5.5
5.5
5.5
5.5
1.0
3.0
0.1
2.0
0.5
V
IN
= V
CC
or V
SS
2.0
0.5
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
-0.6
V
CC
x 0.7
20
0.10
0.05
2.0
35
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
µA
µA
µA
V
V
V
V
µA
µA
Units
V
V
V
V
mA
mA
µA
I
SB2
I
SB3
I
SB4
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Notes:
1. V
IL
min and V
IH
max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from T
A
= -40°C to +85°C, V
CC
= +1.8V to +5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted).
1.8-volt
Symbol
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Note:
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
(1)
Clock Low to Data Out Valid
Time the bus must be free
before a new transmission can start
(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
1M
4.7
100
20
1M
0.1
4.7
4.0
4.7
0
200
1.0
300
4.7
100
10
1M
4.7
4.0
100
4.5
0.1
4.7
4.0
4.7
0
200
1.0
300
0.6
50
10
Min
Max
100
4.7
4.0
100
4.5
0.1
1.2
0.6
0.6
0
100
0.3
300
2.7-, 2.5-volt
Min
Max
100
1.2
0.6
50
0.9
5.0-volt
Min
Max
400
Units
kHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write Cycles
1. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION:
A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION:
A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE:
All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE:
The AT24C32/64 features a low power
standby mode which is enabled: a) upon power-up and b)
after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET:
After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle
while SCL is high and then (c) create a start condition as
SDA is high.
4
AT24C32/64
AT24C32/64
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
t
WR(1)
Note:
1.
The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
5
京公网安备 11010802033920号
EEWORLD
