MKT 1826
Vishay Roederstein
Metallized Polyester Film Capacitor
Quality Assessment: CECC 30 401-059
MAIN APPLICATIONS:
Blocking, bypassing, filtering and timing, high frequency
coupling and decoupling of fast digital circuits.
Interference suppression in low voltage applications. High
pulse load. High temperature operations.
Dimensions in millimeters
L
Max.
W
Max.
Marking
MARKING:
Manufacturer's logo/type/C-value/rated voltage/tolerance/
date of manufacture
DIELECTRIC:
Polyester film
0.5
±
0.1
H
Max.
ELECTRODES:
Vacuum deposited aluminum
COATING:
Flame retardant plastic case (UL-class 94 V-0), green,
epoxy resin sealed
pcm
5.0
±
0.4
±
0.4
Ø 0.5
6.0
-1
CONSTRUCTION:
Stacked metallized polyester film
TIME CONSTANT:
Measured at 100 VDC (50 VDC and 63 VDC series
measured at 50 VDC, 40 VDC measured with U
R
) after
one minute
LEADS:
Tinned wire
IEC TEST CLASSIFICATION:
55/125/56, according to IEC 60068
55/100/21 (for 4.7µF/40 VDC)
For 0.33
µ
F < C
≤
3.3
µ
F and U
R
≤
100 VDC:
5000 s minimum value (15,000 s typical value)
OPERATING TEMPERATURE RANGE:
- 55°C to + 125°C
- 55°C to + 100°C (for 4.7µF/40 VDC)
For C > 3.3
µ
F and U
R
≤
100 VDC:
CAPACITANCE DRIFT:
1250 s minimum value (10,000 s typical value)
Up to + 40°C,
±
1.5% for a period of two years
CAPACITANCE RANGE:
1000pF to 4.7µF
CAPACITANCE TOLERANCES:
±
20% (M),
±
10% (K),
±
5% (J)
DERATING FOR DC AND AC.
CATEGORY VOLTAGE U
C
:
At + 85°C: U
C
= 1.0 U
R
At + 100°C: U
C
= 0.8 U
R
At + 125°C: U
C
= 0.5 U
R
(maximum 1000 h)
RATED VOLTAGES (U
R
):
40 VDC, 50 VDC, 63 VDC, 100 VDC, 250 VDC
PERMISSIBLE AC VOLTAGES (RMS) UP TO 60Hz:
25 VAC, 30 VAC, 40 VAC, 63 VAC, 160 VAC
SELF INDUCTANCE:
~ 6 nH measured with 2mm long leads
TEST VOLTAGE (ELECTRODE/ELECTRODE):
1.6 x U
R
for 2 sec.
PULL TEST ON LEADS:
≥
30 N in direction of leads according to IEC 60068-2-21
INSULATION RESISTANCE:
Measured at 100 VDC (50 VDC and 63 VDC series
measured at 50 VDC) after one minute
RELIABILITY:
Operational life > 300,000 h
Failure rate < 2 FIT (40°C and 0.5 x U
R
)
For further details, please refer to the general information
provided in this catalog.
For C
≤
0.33
µ
F and U
R
> 100 VDC:
For C
≤
0.33
µ
F and U
R
≤
100 VDC:
30,000 MΩ minimum value (100,000 MΩ typical value)
15,000 MΩ minimum value (100,000 MΩ typical value)
MAXIMUM PULSE RISE TIME
PCM
(mm)
5.0
40 VDC
120
Maximum pulse rise time d
v
/d
t
[V/
µ
s]
50 VDC
160
63 VDC
200
100 VDC
240
250 VDC
350
If the maximum pulse voltage is less than the rated voltage higher d
v
/d
t
values can be permitted.
www.vishay.com
52
Document Number 26007
Revision 15-Dec-00
FPGA/CPLD
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