S29AL004D
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
Datasheet
Distinctive Characteristics
Architectural Advantages
Single power supply operation
— 2.7 to 3.6 volt read and write operations for battery-
powered applications
ADVANCE
Performance Characteristics
High performance
— Access times as fast as 70 ns
Manufactured on 200nm process technology
— Compatible with 320nm Am29LV400B and
MBM29LV400T/BC
Ultra low power consumption (typical values
at 5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 20 mA program/erase current
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven
64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and seven
32 Kword sectors (word mode)
— Supports full chip erase
Cycling Endurance: 1,000,000 cycles per
sector typical
Data Retention: 20 years typical
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Package Options
48-ball FBGA
48-pin TSOP
44-pin SO
Top or bottom boot block configurations
available
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
Software Features
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
Hardware Features
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Sector Protection features
— A hardware method of locking a sector to prevent any
program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array
data
Publication Number
S29AL004D_00
Revision
A
Amendment
0
Issue Date
November 12, 2004
General Description
The S29AL004D is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288
bytes or 262,144 words. The device is offered in 48-ball FBGA, 44-pin SO, and
48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0
volt V
CC
supply to perform read, program, and erase operations. A standard
EPROM programmer can also be used to program and erase the device.
This device is manufactured using Spansion’s 200nm process technology, and of-
fers all the features and benefits of the Am29LV400B and MBM29LV400T/BC,
which were manufactured using 320nm process technology.
The standard device offers access times of 70 and 90ns, allowing high speed mi-
croprocessors to operate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
The device requires only a
single 3.0 volt power supply
for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-
supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an in-
ternal state-machine that controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This
initiates the
Embedded Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass
mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates
the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the
erase operation. During erase, the device automatically times the erase pulse
widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by
observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (tog-
gle)
status bits.
After a program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The
sector erase architecture
allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. The
hardware sector
protection
feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.
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S29AL004D
S29AL004D_00_A0 November 12, 2004
P r e l i m i n a r y
The
Erase Suspend
feature enables the user to put erase on hold for any period
of time to read data from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the
internal state machine to reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also reset the device, enabling
the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consump-
tion is greatly reduced in both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing ex-
perience to produce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits within a sector simulta-
neously via Fowler-Nordheim tunneling. The data is programmed using hot
electron injection.
November 12, 2004 S29AL004D_00_A0
S29AL004D
3
Table Of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Special Handling Instructions for FBGA Package ...........................7
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Standard Products .................................................................................. 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 10
Table 1. S29AL004D Device Bus Operations .........................10
Reading Toggle Bits DQ6/DQ2 ........................................................ 28
DQ5: Exceeded Timing Limits ..........................................................28
DQ3: Sector Erase Timer ..................................................................28
Figure 6. Toggle Bit Algorithm ............................................ 29
Table 6. Write Operation Status ......................................... 30
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 31
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7. Maximum Negative Overshoot Waveform................ 31
Figure 8. Maximum Positive Overshoot Waveform ................. 31
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 32
CMOS Compatible ............................................................................... 32
Figure 9. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ................................................. 33
Figure 10. Typical I
CC1
vs. Frequency .................................. 34
Figure 11. Test Setup ........................................................ 35
Table 7. Test Specifications ............................................... 35
Word/Byte Configuration ...................................................................10
Requirements for Reading Array Data ...........................................10
Writing Commands/Command Sequences .................................... 11
Program and Erase Operation Status ............................................... 11
Standby Mode .......................................................................................... 11
Automatic Sleep Mode ......................................................................... 12
RESET#: Hardware Reset Pin ............................................................ 12
Output Disable Mode ........................................................................... 12
Table 2. S29AL004D Top Boot Block Sector Addresses ...........13
Table 3. S29AL004D Bottom Boot Block Sector Addresses ......13
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Key to Switching Waveforms. . . . . . . . . . . . . . . . 36
Figure 12. Input Waveforms and Measurement Levels............ 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 37
Read Operations ....................................................................................37
Figure 13. Read Operations Timings .................................... 37
Autoselect Mode ................................................................................... 13
Table 4. S29AL004D Autoselect Codes (High Voltage Method) .14
Hardware Reset (RESET#) ................................................................ 38
Figure 14. RESET# Timings ................................................ 38
Sector Protection/Unprotection ....................................................... 14
Temporary Sector Unprotect ........................................................... 14
Figure 1. Temporary Sector Unprotect Operation................... 15
Figure 2. In-System Sector Protect/Sector
Unprotect Algorithms ........................................................ 16
Word/Byte Configuration (BYTE#) ............................................. 39
Figure 15. BYTE# Timings for Read Operations ..................... 40
Figure 16. BYTE# Timings for Write Operations..................... 40
Erase/Program Operations ................................................................. 41
Figure 17. Program Operation Timings ................................. 42
Figure 18. Chip/Sector Erase Operation Timings.................... 43
Figure 19. Data# Polling Timings
(During Embedded Algorithms)........................................... 44
Figure 20. Toggle Bit Timings (During Embedded Algorithms) . 44
Figure 21. DQ2 vs. DQ6..................................................... 45
Hardware Data Protection ................................................................. 17
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 17
Reading Array Data .............................................................................. 17
Reset Command ....................................................................................18
Autoselect Command Sequence .......................................................18
Word/Byte Program Command Sequence ....................................18
Figure 3. Program Operation .............................................. 20
Temporary Sector Unprotect .......................................................... 45
Figure 22. Temporary Sector Unprotect Timing Diagram......... 45
Figure 23. Sector Protect/Unprotect Timing Diagram.............. 46
Chip Erase Command Sequence ......................................................20
Sector Erase Command Sequence ................................................... 21
Erase Suspend/Erase Resume Commands ..................................... 21
Figure 4. Erase Operation .................................................. 23
Table 5. S29AL004D Command Definitions ...........................24
Alternate CE# Controlled Erase/Program Operations ............ 47
Figure 24. Alternate CE# Controlled Write Operation Timings.. 48
Write Operation Status . . . . . . . . . . . . . . . . . . . . 25
DQ7: Data# Polling .............................................................................. 25
Figure 5. Data# Polling Algorithm ....................................... 26
RY/BY#: Ready/Busy# ......................................................................... 26
DQ6: Toggle Bit I .................................................................................. 27
DQ2: Toggle Bit II ................................................................................ 27
Erase and Programming Performance . . . . . . . . .49
TSOP, SO and BGA Pin Capacitance . . . . . . . . . 49
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .50
TS 048—48-Pin Standard TSOP ..................................................... 50
VBK 048 - 48 Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 x 6.15 mm ......................................................................................... 51
SO 044—44-Pin Small Outline Package ....................................... 52
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 53
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S29AL004D
S29AL004D_00_A0 November 12, 2004
P r e l i m i n a r y
Product Selector Guide
Family Part Number
Speed Options
Full Voltage Range: V
CC
= 2.7–3.6 V
70
70
70
30
S29AL004D
90
90
90
35
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max OE# access time, ns (t
OE
)
Note:
See “AC Characteristics” for full specifications.
Block Diagram
RY/BY#
V
CC
V
SS
RESET#
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
DQ0–DQ15 (A-1)
WE#
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Address Latch
Y-Decoder
Y-Gating
Timer
X-Decoder
Cell Matrix
A0–A17
November 12, 2004 S29AL004D_00_A0
S29AL004D
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