The AT28C040 is accessed like a static RAM for the read
or write cycle without the need for external components.
The device contains a 256-byte page register to allow writ-
ing of up to 256 bytes simultaneously. During a write cycle,
the address and 1 to 256 bytes of data are internally
latched, freeing the address and data bus for other opera-
tions. Following the initiation of a write cycle, the device will
automatically write the latched data using an internal con-
trol timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has
been detected, a new access for a read or write can begin.
Atmel's AT28C040 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved data
retention characteristics. An optional software data protec-
tion mechanism is available to guard against inadvertent
writes. The device also includes an extra 256 bytes of
E
2
PROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
2
AT28C040
AT28C040
Device Operation
READ:
The AT28C040 is accessed like a static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention in their systems.
BYTE WRITE:
A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cycle.
The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising
edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the duration
of t
WC
, a read operation will effectively be a polling opera-
tion.
PAGE WRITE:
The page write operation of the AT28C040
allows 1 to 256 bytes of data to be written into the device
during a single internal programming period. A page write
operation is initiated in the same manner as a byte write;
the first byte written can then be followed by 1 to 255 addi-
tional bytes. Each successive byte must be written within
150
µs
(t
BLC
) of the previous byte. If the t
BLC
limit is
exceeded, the AT28C040 will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A8 - A18 inputs. For
each WE high to low transition during the page write opera-
tion, A8 - A18 must be the same.
The A0 to A7 inputs specify which bytes within the page are
to be written. The bytes may be loaded in any order and
may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary
cycling of other bytes within the page does not occur.
DATA POLLING:
The AT28C040 features DATA Polling to
indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write
cycle.
TOGGLE BIT:
In addition to DATA Polling, the AT28C040
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling
between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION:
If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION:
Hardware features protect
against inadvertent writes to the AT28C040 in the following
ways: (a) V
CC
sense - if V
CC
is below 3.8V (typical) the write
function is inhibited; (b) V
CC
power-on delay - once V
CC
has
reached 3.8V the device will automatically time out 5 ms
(typical) before allowing a write: (c) write inhibit - holding
any one of OE low, CE high or WE high inhibits write
cycles; (d) noise filter - pulses of less than 15 ns (typical)
on the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION:
A software controlled
data protection feature has been implemented on the
AT28C040. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C040 is
shipped from Atmel with SDP disabled.
SDP is enabled when the host system issues a series of
three write commands; three specific bytes of data are writ-
ten to three specific addresses (refer to Software Data Pro-
tection Algorithm). After writing the 3-byte command
sequence and after t
WC
, the entire AT28C040 will be pro-
tected against inadvertent write operations. It should be
noted that once protected, the host can still perform a byte
or page write to the AT28C040. To do so, the same 3-byte
command sequence used to enable SDP must precede the
data to be written.
Once set, SDP will remain active unless the disable com-
mand sequence is issued. Power transitions do not disable
SDP, and SDP will protect the AT28C040 during power-up
and power-down conditions. All command sequences must
conform to the page write timing specifications. The data in
the enable and disable command sequences is not written
to the device, and the memory addresses used in the
sequence may be written with data in either a byte or page
write operation.
After setting SDP, any attempt to write to the device without
the 3-byte command sequence will start the internal write
timers. No data will be written to the device; however, for
the duration of t
WC
, read operations will effectively be poll-
ing operations.
DEVICE IDENTIFICATION:
An extra 256 bytes of
E
2
PROM memory are available to the user for device iden-
tification. By raising A9 to 12V
±
0.5V and using address
locations 7FF80H to 7FFFFH, the bytes may be written to
or read from in the same manner as the regular memory
array.
OPTIONAL CHIP ERASE MODE:
The entire device can
be erased using a 6-byte software erase code. Please see
Software Chip Erase application note for details.
3
京公网安备 11010802033920号
EEWORLD
