AGLN250V2-QN100 datasheet, PDF

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AGLN250V2-QN100: DescriptionField Programmable Gate Array, 6144-Cell, CMOS, PBCC100, 8 X 8 MM, 0.85 HEIGHT, 0.50 MM PITCH, QFN-100; CategoryProgrammable logic devices Programmable logic; File Size4MB，114 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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AGLN250V2-QN100 Overview

Field Programmable Gate Array, 6144-Cell, CMOS, PBCC100, 8 X 8 MM, 0.85 HEIGHT, 0.50 MM PITCH, QFN-100

AGLN250V2-QN100 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Actel
package instruction	8 X 8 MM, 0.85 HEIGHT, 0.50 MM PITCH, QFN-100
Reach Compliance Code	compli
JESD-30 code	S-PBCC-B100
Number of entries	68
Number of logical units	6144
Output times	68
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LGA
Encapsulate equivalent code	LGA100(UNSPEC)
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.2/1.5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BUTT
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED

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Advance v0.4

IGLOO nano Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

nanoPower Consumption—Industry’s Lowest Power

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

Low-Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze

Mode

•

Advanced I/Os

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

†

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Small Footprint Packages

• As Small as 3x3 mm in Size

Wide Range of Features

• 10 k to 250 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

• FlashLock

to Secure FPGA Contents

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except × 18 organization)

†

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Enhanced Commercial Temperature Range

• –20°C to +70°C

IGLOO nano Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

VersaNet

I/O Banks

Maximum User I/Os

Maximum User I/Os (Known Good Die)

Package Pins

UC/CS

QFN

VQFP

AGLN010

10 k

260

–

UC36

QN48

AGLN015

15 k

128

384

–

AGLN020

20 k

172

520

–

AGLN030

30 k

256

768

–

AGLN060

60 k

512

1,536

Yes

CS81

QN100

VQ100

AGLN125

125 k

1,024

3,072

Yes

CS81

QN100

VQ100

AGLN250

250 k

2,048

6,144

Yes

CS81

QN100

VQ100

bits)

Integrated PLL in CCCs

Globals

QN68

UC81, CS81 UC81, CS81

QN68

QN48, QN68

VQ100

Notes:

1. AGLN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices. Refer

"IGLOO nano Ordering Information" on page III.

2. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs. AGLN030 and smaller devices do not support this

feature

3. Six chip (main) and three quadrant global networks are available for AGLN060 and above.

4. For higher densities and support of additional features, refer to the

IGLOO

and

IGLOOe

handbooks.

† AGLN030 and smaller devices do not support this feature.

December 2008

1 – IGLOO nano Device Overview

General Description

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a

single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced

features.

The Flash*Freeze technology used in IGLOO nano devices enables entering and exiting an ultra-

low-power mode that consumes nanoPower while retaining SRAM and register data. Flash*Freeze

technology simplifies power management through I/O and clock management with rapid recovery

to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption while the

IGLOO nano device is completely functional in the system. This allows the IGLOO nano device to

control system power management based on external inputs (e.g., scanning for keyboard stimulus)

while consuming minimal power.

Nonvolatile flash technology gives IGLOO nano devices the advantage of being a secure, low-

power, single-chip solution that is live at power-up (LAPU). The IGLOO nano device is

reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOO nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well

as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGLN030 and

smaller devices have no PLL or RAM support. IGLOO nano devices have up to 250 k system gates,

supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.

IGLOO nano devices increase the breadth of the IGLOO product line by adding new features and

packages for greater customer value in high volume consumer, portable, and battery-backed

markets. Features such as smaller footprint packages designed with two-layer PCBs in mind, power

consumption measured in nanoPower, Schmitt trigger, and bus hold functionality make these

devices ideal for deployment in applications that require high levels of flexibility and low cost.

Flash*Freeze Technology

The IGLOO nano device offers unique Flash*Freeze technology, allowing the device to enter and

exit ultra-low-power Flash*Freeze mode. IGLOO nano devices do not need additional components

to turn off I/Os or clocks while retaining the design information, SRAM content, and registers.

Flash*Freeze technology is combined with in-system programmability, which enables users to

quickly and easily upgrade and update their designs in the final stages of manufacturing or in the

field. The ability of IGLOO nano V2 devices to support a wide range of core voltage (1.2 V to 1.5 V)

allows further reduction in power consumption, thus achieving the lowest total system power.

During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state,

tristate, HIGH, or LOW.

The availability of low-power modes, combined with reprogrammability, a single-chip and single-

voltage solution, and small-footprint packages make IGLOO nano devices the best fit for portable

electronics.

A dv a n c e v 0. 4

1-1

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