Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
1
FEATURES
3
GENERAL DESCRIPTION
TDA5153
•
Designed for 4 (TDA5153BG) or 6 dual-stripe
MR-read/inductive write heads
•
Current bias-current sense architecture
•
Single supply voltage (5.0 V
±10%);
a separate write
drivers supply pin can be biased from V
CC
to 8 V +10%
•
MR elements connected to ground (GND)
•
Equal bias currents in the two MR stripes of each head
•
On-chip AC couplings eliminate MR head DC offset
•
3-wire serial interface for programming
•
Programmable high-frequency zero-pole gain boost
•
Programmable write driver compensation capacitance
•
Programmable MR bias currents and write currents
•
1-bit programmable read gain
•
Sleep, standby, active and test modes available
•
Measurement of head resistances in test mode
•
In test mode, one MR bias current may be forced to a
minimum current
•
Short write current rise and fall times with near rail-to-rail
voltage swing
•
Head unsafe pin for signalling of abnormal conditions
and behaviour
•
Low supply voltage write-current inhibit (active or
inactive)
•
Supports servo writing
•
Provides temperature monitor
•
Thermal asperity detection with programmable
threshold level
•
Requires only one external resistor.
2
APPLICATIONS
The 5.0 V pre-amplifier for HDD described here is
designed for five terminals, dual stripe Magneto-Resistive
(MR)-read/inductive-write heads. The disks of the disk
drive are connected to ground. To avoid voltage
break-through between the heads and the disk, the MR
elements of the heads are also connected to ground. The
symmetry of the dual-stripe head-amplifier combination
automatically distinguishes between the differential
signals such as signals and the common-mode effects like
interference. The latter are rejected by the amplifier.
The IC incorporates read amplifiers, write amplifiers, serial
interface, digital-to-analog converters, reference and
control circuits which operate on a single supply voltage of
5 V
±10%.
The output drivers have a separate supply
voltage pin which can be connected to a higher supply
voltage of up to 8 V +10%. The complementary output
stages of the write amplifier allow writing with near
rail-to-rail peak voltages across the inductive write head.
The read amplifier has a low input impedance. The DC
offset between the two stripes of the MR head is eliminated
using on-chip AC coupling. Fast settling features are used
to keep the transients short. As an option, the read
amplifier may be left biased during writing so as to reduce
the duration of these transients even more. Series
inductance in the leads between the amplifier and MR
heads influences the bandwidth which can be
compensated by using a programmable high-frequency
gain-boost (HF zero). HF noise and bandwidth can be
attenuated using a programmable high-frequency
gain-attenuator (HF pole).
On-chip digital-to-analog converters for MR bias currents
and write currents are programmed via a 3-wire serial
interface. Head selection, mode control, testing and servo
writing can also be programmed using the serial interface.
In sleep mode the CMOS serial interface is operational.
Figure 1 shows the block diagram of the device.
•
Hard Disk Drive (HDD).
4
ORDERING INFORMATION
TYPE
NUMBER
TDA5153X
TDA5153AG;
TDA5153BG
PACKAGE
NAME
−
LQFP48
naked die
plastic low profile quad flat package; 48 leads; body 7
×
7
×
1.4 mm
DESCRIPTION
VERSION
−
SOT313-2
1997 Jul 02
3
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
5
QUICK REFERENCE DATA
SYMBOL
V
CC
V
CC(WD)
F
V
nir
G
v(dif)
PARAMETER
supply voltage
write drivers supply voltage
noise figure
R
MR
= 28
Ω;
I
MR
= 10 mA;
T
amb
= 25
°C;
f = 20 MHz
CONDITIONS
MIN.
4.5
V
CC
−
−
TYP.
5.0
8.0
3.0
0.9
TDA5153
MAX.
5.5
8.8
3.2
1.0
UNIT
V
V
dB
nV/√Hz
input referred noise voltage; see R
MR
= 28
Ω;
I
MR
= 10 mA;
note 3 in Chapter 13
T
amb
= 25
°C;
f = 20 MHz
differential voltage gain
from head inputs to RDx, RDy;
R
MR
= 28
Ω;
I
MR
= 10 mA
d4 = logic 0
d4 = logic 1
−
−
−
−
−
−
−
160
226
220
45
25
80
50
−
−
−
−
−
−
−
MHz
dB
dB
dB
dB
B
−3
db
CMRR
PSRR
−3
dB frequency bandwidth
common mode rejection ratio;
R
MR
mismatch <5%
power supply rejection ratio
(input referred);
R
MR
mismatch <5%
rise/fall times (10% to 90%)
upper bandwidth without gain
boost (4 nH lead inductance)
I
MR
= 10 mA; f < 1 MHz
I
MR
= 10 mA; f < 100 MHz
f < 1 MHz
f < 100 MHz
L
h
= 150 nH; I
WR
= 35 mA;
f = 20 MHz
V
CC(WD)
= 8.0 V
V
CC(WD)
= 6.5 V
t
r
, t
f
−
−
5
20
−
−
−
−
−
−
1.8
2.1
20.5
51
25
ns
ns
mA
mA
MHz
I
MR(PR)
programming MR bias current
R
ext
= 10 kΩ
R
ext
= 10 kΩ
I
WR(PR)(b-p)
programming write current
range (base-to-peak)
f
SCLK
serial interface clock rate
1997 Jul 02
4
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