5962H9651802Q9A datasheet, PDF

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5962H9651802Q9A: DescriptionAND Gate, AC Series, 4-Func, 2-Input, CMOS, DIE-14; Categorylogic logic; File Size281KB，23 Pages; ManufacturerCobham PLC

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5962H9651802Q9A Overview

AND Gate, AC Series, 4-Func, 2-Input, CMOS, DIE-14

5962H9651802Q9A Parametric

Parameter Name	Attribute value
Maker	Cobham PLC
package instruction	DIE, DIE OR CHIP
Reach Compliance Code	unknow
series	AC
JESD-30 code	R-XUUC-N14
Load capacitance (CL)	50 pF
Logic integrated circuit type	AND GATE
MaximumI(ol)	0.006 A
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	UNSPECIFIED
encapsulated code	DIE
Encapsulate equivalent code	DIE OR CHIP
Package shape	RECTANGULAR
Package form	UNCASED CHIP
power supply	3.3/5 V
Prop。Delay @ Nom-Su	19 ns
propagation delay (tpd)	19 ns
Certification status	Qualified
Schmitt trigger	NO
Filter level	MIL-PRF-38535 Class Q
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.6 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal location	UPPER
total dose	1M Rad(Si) V

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REVISIONS

LTR

DESCRIPTION

Changes in accordance with NOR 5962-R075-97. - jak

Incorporate NOR and update boilerplate to latest MIL-PRF-38535

requirements. - CFS

Correct the title to accurately describe the device function. Update boilerplate

to the latest MIL-PRF-38535 requirements. - jak

Add device types 02 and 03. Add die appendix - jak

Change footnote 6 in section 1.5, herein. - jak

To change RHA level “H” to “G” for device type 01. Update radiation features

in section 1.5 and table IB. Update boilerplate paragraphs to current

requirements of MIL-PRF-38535 - MAA

Add equivalent test circuit and footnote 5 in figure 4. Delete class M

requirements. – MAA

DATE (YR-MO-DA)

96-11-25

01-06-11

07-09-14

08-05-05

08-12-03

11-03-17

APPROVED

Monica L. Poelking

Thomas M. Hess

David J. Corbett

12-07-24

Thomas M. Hess

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Larry T. Gauder

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

CHECKED BY

Thanh V. Nguyen

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

http://www.landandmaritime.dla.mil

APPROVED BY

Monica L. Poelking

DRAWING APPROVAL DATE

96-06-12

REVISION LEVEL

MICROCIRCUIT, DIGITAL, ADVANCED CMOS,

RADIATION HARDENED, QUADRUPLE

2-INPUT AND GATE, MONOLITHIC SILICON

SIZE

CAGE CODE

67268

SHEET

5962-96518

1 OF 22

DSCC FORM 2233

APR 97

5962-E377-12

1.3 Absolute maximum ratings. 1/, 2/, 3/

Supply voltage range (V

) .................................................................................. -0.3 V dc to +7.0 V dc

DC input voltage range (V

) ................................................................................ -0.3 V dc to V

+ 0.3 V dc

DC output voltage range (V

OUT

) ........................................................................... -0.3 V dc to V

+ 0.3 V dc

DC input current, any one input (I

).....................................................................

±10

Latch-up immunity current (I

) ............................................................................

±150

Storage temperature range (T

STG

) ....................................................................... -65°C to +150°C

Lead temperature (soldering, 5 seconds) ............................................................ +300°C

Thermal resistance, junction-to-case (θ

Device type 01, case outlines C and X .............................................................. See MIL-STD-1835

Device types 02 and 03, case outline X ............................................................. 15.5°C/W

Junction temperature (T

) .................................................................................... +175°C

Maximum package power dissipation (P

Device type 01 ................................................................................................... 1.0 W

Device type 02 and 03 ....................................................................................... 3.2 W 4/

1.4 Recommended operating conditions. 2/, 3/

Supply voltage range (V

): ................................................................................

Device type 01 ................................................................................................... +4.5 V dc to +5.5 V dc

Device type 02 and 03 ....................................................................................... +3.0 V dc to +5.5 V dc

Input voltage range (V

) ..................................................................................... +0.0 V dc to V

Output voltage range (V

OUT

) ................................................................................ +0.0 V dc to V

Case operating temperature range (T

) .............................................................. -55°C to +125°C

Maximum input rise or fall time rate at V

= 4.5 V (t

, t

) ....................................1 ns/V 5/

1.5 Radiation features.

Maximum total dose available:

Device type 01 (dose rate = 50 – 300 rads (Si)/s) ............................................ 5 x 10 rads (Si)

Device type 02 (effective dose rate = 1 rad (Si)/s) ........................................... 1 x 10 rad (Si) 6/

Device type 03 (dose rate = 50 – 300 rads (Si)/s) ............................................ 5 x 10 rads (Si)

Single event phenomenon (SEP) :

Device type 01:

No upsets (SEU) at effective LET (see 4.4.4.4)............................................... ≤ 80 MeV/(mg/cm ) 8/

No latch-up (SEL) at effective LET (see 4.4.4.4) ............................................. ≤ 120 MeV/(mg/cm ) 8/

Device types 02 and 03:

No upsets (SEU) at effective LET (see 4.4.4.4)............................................... ≤ 108 MeV/(mg/cm ) 8/

No latch-up (SEL) at effective LET (see 4.4.4.4) ............................................. ≤ 120 MeV/(mg/cm ) 8/

Dose rate upset (20 ns pulse) ............................................................................ ≥ 1 x 10 rad (Si)/s 8/ 9/

Dose rate induced latch-up ................................................................................. None 8/

Dose rate survivability ....................................................................................... ≥ 1 x 10 rad (Si)/s 8/

Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the

maximum levels may degrade performance and affect reliability.

Unless otherwise specified, all voltages are referenced to V

The limits for the parameters specified herein shall apply over the full specified V

range and case temperature range

of -55°C to +125°C unless otherwise specified.

Per MIL-STD-883 method 1012.1 section 3.4.1, P

(Package) = (T

(max) - T

(max)) .

Derate system propagation delays by difference in rise time to switch point for t

or t

1 ns/V.

Device type 02 is irradiated at dose rate = 50 - 300 rads (Si)/s in accordance with MIL-STD-883, method 1019,

condition A, and is guaranteed to a maximum total dose specified. The effective dose rate after extended room

temperature anneal = 1 rad (Si)/s per MIL-STD-883, method 1019, condition A, section 3.11.2. The total dose

specification for these devices only applies to the specified effective dose rate, or lower, environment.

Radiation testing is performed on the standard evaluation circuit (SEC).

Limits are guaranteed by design or process, but not production tested unless specified by the customer through the

purchase order or contract.

This limit is applicable for device type 01, 02, and 03 with V

≥ 4.5 V. Device types 02 and 03 do not meet this limit at

< 4.5 V.

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-96518

SHEET

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICATION

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-883 -

MIL-STD-1835 -

Test Method Standard Microcircuits.

Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 -

MIL-HDBK-780 -

List of Standard Microcircuit Drawings.

Standard Microcircuit Drawings.

(Copies of these documents are available online at

https://assist.dla.mil/quicksearch/

or from the Standardization Document

Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.

Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.

ASTM INTERNATIONAL (ASTM)

ASTM F1192

Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion

Irradiation of semiconductor Devices.

(Copies of these documents are available online at

http://www.astm.org

or from ASTM International, 100 Barr Harbor Drive,

P.O. Box C700, West Conshohocken, PA, 19428-2959).

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific

exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

MIL-PRF-38535 and herein for device classes Q and V.

3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Truth table. The truth table shall be as specified on figure 2.

3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.

3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4.

3.2.6 Irradiation test connections. The irradiation test connections shall be maintained by the manufacturer under document

revision level control and shall be made available to the preparing and acquiring activity upon request.

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-96518

SHEET

5962H9651802Q9A Related Products

	5962H9651802Q9A	5962G9651801VXC	5962G9651801QXC	5962G9651801QXA	5962G9651801VXA	5962H9651802V9A	5962G9651803Q9A	5962G9651803V9A
Description	AND Gate, AC Series, 4-Func, 2-Input, CMOS, DIE-14	AND Gate, AC Series, 4-Func, 2-Input, CMOS, CDFP14, CERAMIC, BOTTOM BRAZED, DFP-14	AND Gate, AC Series, 4-Func, 2-Input, CMOS, CDFP14, CERAMIC, BOTTOM BRAZED, DFP-14	AND Gate, AC Series, 4-Func, 2-Input, CMOS, CDFP14, CERAMIC, BOTTOM BRAZED, DFP-14	AND Gate, AC Series, 4-Func, 2-Input, CMOS, CDFP14, CERAMIC, BOTTOM BRAZED, DFP-14	AND Gate, AC Series, 4-Func, 2-Input, CMOS, DIE-14	AND Gate, AC Series, 4-Func, 2-Input, CMOS, DIE-14	AND Gate, AC Series, 4-Func, 2-Input, CMOS, DIE-14
package instruction	DIE, DIE OR CHIP	DFP, FL14,.3	DFP, FL14,.3	DFP, FL14,.3	CERAMIC, BOTTOM BRAZED, DFP-14	DIE, DIE OR CHIP	DIE, DIE OR CHIP	DIE, DIE OR CHIP
Reach Compliance Code	unknow	unknown	unknown	unknown	unknown	unknown	unknown	unknown
series	AC	AC	AC	AC	AC	AC	AC	AC
JESD-30 code	R-XUUC-N14	R-CDFP-F14	R-CDFP-F14	R-CDFP-F14	R-CDFP-F14	R-XUUC-N14	R-XUUC-N14	R-XUUC-N14
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE
MaximumI(ol)	0.006 A	0.008 A	0.008 A	0.008 A	0.008 A	0.006 A	0.006 A	0.006 A
Number of functions	4	4	4	4	4	4	4	4
Number of entries	2	2	2	2	2	2	2	2
Number of terminals	14	14	14	14	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIE	DFP	DFP	DFP	DFP	DIE	DIE	DIE
Encapsulate equivalent code	DIE OR CHIP	FL14,.3	FL14,.3	FL14,.3	FL14,.3	DIE OR CHIP	DIE OR CHIP	DIE OR CHIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	UNCASED CHIP	FLATPACK	FLATPACK	FLATPACK	FLATPACK	UNCASED CHIP	UNCASED CHIP	UNCASED CHIP
power supply	3.3/5 V	5 V	5 V	5 V	5 V	3.3/5 V	3.3/5 V	3.3/5 V
propagation delay (tpd)	19 ns	13 ns	13 ns	13 ns	13 ns	19 ns	19 ns	19 ns
Certification status	Qualified	Qualified	Qualified	Qualified	Qualified	Qualified	Qualified	Qualified
Schmitt trigger	NO	NO	NO	NO	NO	NO	NO	NO
Filter level	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class V	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class V
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	3 V	4.5 V	4.5 V	4.5 V	4.5 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.6 V	5 V	5 V	5 V	5 V	3.6 V	3.6 V	3.6 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	NO LEAD	FLAT	FLAT	FLAT	FLAT	NO LEAD	NO LEAD	NO LEAD
Terminal location	UPPER	DUAL	DUAL	DUAL	DUAL	UPPER	UPPER	UPPER
total dose	1M Rad(Si) V	500k Rad(Si) V	500k Rad(Si) V	500k Rad(Si) V	500k Rad(Si) V	1M Rad(Si) V	500k Rad(Si) V	500k Rad(Si) V
Maker	Cobham PLC	-	-	-	Cobham PLC	Cobham PLC	Cobham PLC	Cobham PLC
Prop。Delay @ Nom-Sup	-	13 ns	13 ns	13 ns	13 ns	19 ns	19 ns	19 ns

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