AT29C512-90PC datasheet, PDF - EEWORLD Datasheet

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AT29C512-90PC: Description64K X 8 FLASH 5V PROM, 90 ns, PQCC32; Categorystorage storage; File Size198KB，18 Pages; ManufacturerAtmel (Microchip)

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AT29C512-90PC Overview

64K X 8 FLASH 5V PROM, 90 ns, PQCC32

AT29C512-90PC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	DIP
package instruction	DIP, DIP32,.6
Contacts	32
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	90 ns
Other features	AUTOMATIC WRITE; HARDWARE & SOFTWARE DATA PROTECTION
command user interface	NO
Data polling	YES
Durability	10000 Write/Erase Cycles
JESD-30 code	R-PDIP-T32
JESD-609 code	e0
length	42.037 mm
memory density	524288 bi
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	512
Number of terminals	32
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP32,.6
Package shape	RECTANGULAR
Package form	IN-LINE
page size	128 words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	4.826 mm
Department size	128
Maximum standby current	0.0001 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	YES
type	NOR TYPE
width	15.24 mm
Maximum write cycle time (tWC)	10 ms

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Features

•

Fast Read Access Time – 70 ns

•

5-volt Only Reprogramming

•

Sector Program Operation

– Single Cycle Reprogram (Erase and Program)

– 512 Sectors (128 Bytes/Sector)

– Internal Address and Data Latches for 128 Bytes

Internal Program Control and Timer

Hardware and Software Data Protection

Fast Sector Program Cycle Time – 10 ms

DATA Polling for End of Program Detection

Low Power Dissipation

– 50 mA Active Current

– 100 µA CMOS Standby Current

Typical Endurance > 10,000 Cycles

Single 5V ± 10% Supply

CMOS and TTL Compatible Inputs and Outputs

Commercial and Industrial Temperature Ranges

Green (Pb/Halide-free) Packaging Option

•

512K (64K x 8)

5-volt Only

Flash Memory

AT29C512

•

1. Description

The AT29C512 is a 5-volt only in-system Flash programmable and erasable read only

memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Man-

ufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers

access times to 70 ns with power dissipation of just 275 mW over the commercial tem-

perature range. When the device is deselected, the CMOS standby current is less

than 100 µA. The device endurance is such that any sector can typically be written to

in excess of 10,000 times.

To allow for simple in-system reprogrammability, the AT29C512 does not require high

input voltages for programming. Five-volt-only commands determine the operation of

the device. Reading data out of the device is similar to reading from an EPROM.

Reprogramming the AT29C512 is performed on a sector basis; 128 bytes of data are

loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128 bytes of data are internally

latched, freeing the address and data bus for other operations. Following the initiation

of a program cycle, the device will automatically erase the sector and then program

the latched data using an internal control timer. The end of a program cycle can be

detected by DATA polling of I/O7. Once the end of a program cycle has been

detected, a new access for a read or program can begin.

0456H–FLASH–2/05

AT29C512

3. Block Diagram

4. Device Operation

4.1

Read

The AT29C512 is accessed like an EPROM. When CE and OE are low and WE is high, the data

stored at the memory location determined by the address pins is asserted on the outputs. The

outputs are put in the high impedance state whenever CE or OE is high. This dual-line control

gives designers flexibility in preventing bus contention.

4.2

Byte Load

Byte loads are used to enter the 128 bytes of a sector to be programmed or the software codes

for data protection. A byte load is performed by applying a low pulse on the WE or CE input with

CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or

WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.

4.3

Program

The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed,

data for the entire sector must be loaded into the device. Any byte that is not loaded during the

programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the

device, they are simultaneously programmed during the internal programming period. After the

first data byte has been loaded into the device, successive bytes are entered in the same man-

ner. Each new byte to be programmed must have its high-to-low transition on WE (or CE) within

150 µs of the low-to-high transition of WE (or CE) of the preceding byte. If a high-to-low transi-

tion is not detected within 150 µs of the last low-to-high transition, the load period will end and

the internal programming period will start. A7 to A15 specify the sector address. The sector

address must be valid during each high-to-low transition of WE (or CE). A0 to A6 specify the

byte address within the sector. The bytes may be loaded in any order; sequential loading is not

required. Once a programming operation has been initiated, and for the duration of t

, a read

operation will effectively be a polling operation.

0456H–FLASH–2/05

4.4

Software Data Protection

A software controlled data protection feature is available on the AT29C512. Once the software

protection is enabled a software algorithm must be issued to the device before a program may

be performed. The software protection feature may be enabled or disabled by the user; when

shipped from Atmel, the software data protection feature is disabled. To enable the software

data protection, a series of three program commands to specific addresses with specific data

must be performed. After the software data protection is enabled the same three program com-

mands must begin each program cycle in order for the programs to occur. All software program

commands must obey the sector program timing specifications. Once set, the software data pro-

tection feature remains active unless its disable command is issued. Power transitions will not

reset the software data protection feature; however, the software feature will guard against inad-

vertent program cycles during power transitions.

Once set, software data protection will remain active unless the disable command sequence is

issued.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will

start the internal write timers. No data will be written to the device; however, for the duration of

, a read operation will effectively be a polling operation.

After the software data protection’s 3-byte command code is given, a byte load is performed by

applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The

address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by

the first rising edge of CE or WE. The 128 bytes of data must be loaded into each sector by the

same procedure as outlined in the program section under device operation.

4.5

Hardware Data Protection

Hardware features protect against inadvertent programs to the AT29C512 in the following ways:

(a) V

sense – if V

is below 3.8V (typical), the program function is inhibited; (b) V

power on

delay – once V

has reached the V

sense level, the device will automatically time out 5 ms

(typical) before programming; (c) Program inhibit – holding any one of OE low, CE high or WE

high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the WE

or CE inputs will not initiate a program cycle.

4.6

Product Identification

The product identification mode identifies the device and manufacturer as Atmel. It may be

accessed by hardware or software operation. The hardware operation mode can be used by an

external programmer to identify the correct programming algorithm for the Atmel product. In

addition, users may wish to use the software product identification mode to identify the part (i.e.,

using the device code), and have the system software use the appropriate sector size for pro-

gram operations. In this manner, the user can have a common board design for 256K to 4-

megabit densities and, with each density’s sector size in a memory map, have the system soft-

ware apply the appropriate sector size.

For details, see Operating Modes (for hardware operation) or Software Product Identification.

The manufacturer and device code is the same for both modes.

AT29C512

0456H–FLASH–2/05

AT29C512-90PC Related Products

	AT29C512-90PC	29C512	AT29C512-12PC	AT29C512-12	AT29C512-15PI	AT29C512-15	AT29C512-70	AT29C512-70PC	AT29C512-15PC	AT29C512-90
Description	64K X 8 FLASH 5V PROM, 90 ns, PQCC32	64K X 8 FLASH 5V PROM, 90 ns, PQCC32	64K X 8 FLASH 5V PROM, 90 ns, PQCC32	64K X 8 FLASH 5V PROM, 90 ns, PQCC32	64K X 8 FLASH 5V PROM, 90 ns, PQCC32	64K X 8 FLASH 5V PROM, 90 ns, PQCC32	64K X 8 FLASH 5V PROM, 90 ns, PQCC32	64K X 8 FLASH 5V PROM, 90 ns, PQCC32	64K X 8 FLASH 5V PROM, 90 ns, PQCC32	64K X 8 FLASH 5V PROM, 90 ns, PQCC32
memory width	8	8	8	8	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1	1	1	1	1
Number of terminals	32	32	32	32	32	32	32	32	32	32
Maximum operating temperature	70 °C	70 Cel	70 °C	70 Cel	85 °C	70 Cel	70 Cel	70 °C	70 °C	70 Cel
Minimum operating temperature	-	0.0 Cel	-	0.0 Cel	-40 °C	0.0 Cel	0.0 Cel	-	-	0.0 Cel
organize	64KX8	64K × 8	64KX8	64K × 8	64KX8	64K × 8	64K × 8	64KX8	64KX8	64K × 8
surface mount	NO	Yes	NO	Yes	NO	Yes	Yes	NO	NO	Yes
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	THROUGH-HOLE	J BEND	THROUGH-HOLE	J BEND	THROUGH-HOLE	J BEND	J BEND	THROUGH-HOLE	THROUGH-HOLE	J BEND
Terminal location	DUAL	Four	DUAL	Four	DUAL	Four	Four	DUAL	DUAL	Four

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