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CD54AC00

Description
AC SERIES, QUAD 2-INPUT NAND GATE, CDIP14
Categorysemiconductor    logic   
File Size25KB,4 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
Download Datasheet Parametric Compare View All

CD54AC00 Overview

AC SERIES, QUAD 2-INPUT NAND GATE, CDIP14

CD54AC00 Parametric

Parameter NameAttribute value
Number of functions4
Number of terminals14
Minimum operating temperature-55 Cel
Maximum operating temperature125 Cel
Rated supply voltage3.3
Minimum supply/operating voltage1.5 V
Maximum supply/operating voltage5.5 V
Processing package descriptionCERAMIC, DIP-14
each_compliYes
stateActive
Logic IC typeNAND GATE
sub_categoryGates
seriesAC
jesd_30_codeR-GDIP-T14
load_capacitance__cl_50 pF
max_i_ol_0.0240 Am
moisture_sensitivity_levelNOT APPLICABLE
Number of inputs2
Packaging MaterialsCERAMIC, GLASS-SEALED
ckage_codeDIP
ckage_equivalence_codeDIP14,.3
packaging shapeRECTANGULAR
Package SizeIN-LINE
cking_methodTUBE
eak_reflow_temperature__cel_NOT APPLICABLE
wer_supplies__v_3.3/5
._delay_nom_su10.2 ns
propagation delay TPD91 ns
qualification_statusCOMMERCIAL
schmitt_triggeNO
screening_level38535Q/M;38534H;883B
seated_height_max5.08 mm
surface mountNO
CraftsmanshipCMOS
Temperature levelMILITARY
terminal coatingNOT SPECIFIED
Terminal formTHROUGH-HOLE
Terminal spacing2.54 mm
Terminal locationDUAL
ime_peak_reflow_temperature_max__s_NOT APPLICABLE
length19.43 mm
width7.62 mm
Semiconductor
CD54AC00F3A,
CD54ACT00F3A
Quad 2-Input NAND Gate
Description
The CD54AC00F3A and CD54ACT00F3A are quad 2-input
NAND gates that utilize the Harris Advanced CMOS Logic
technology.
July 1998
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
• Meets JEDEC Standard No. 20
• SCR - Latch-Up-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST/A/S with Significantly Reduced
Power Consumption
• Functionally and Pin-Compatible with Industry 54
Bipolar Types in the FAST, AS and S Series
• Balanced Propagation Delays
• Military Operating Temperature Range
- Ceramic (CERDIP) 54 Series: . . . . . . . . -55 to 125
o
C
±24mA
Output Drive Current, Drives 75Ω Lines with-
out Need for Terminations
• Fan Out (Over Temperature)
- ACL Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400
- FAST Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
- AS Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
• Balanced Noise Immunity at 30% of Supply for AC
Types
• Supply Voltage Range
- AC Types . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 5.5V
- ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Ordering Information
PART NUMBER
CD54AC00F3A
CD54ACT00F3A
NOTE:
1. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
TEMP.
RANGE (
o
C)
-55 to 125
-55 to 125
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
PKG.
NO.
F14.3
F14.3
Functional Diagram
1A
1B
2A
2B
3B
3A
4B
4A
1
2
4
5
9
10
12
13
11
3
6
8
3Y
4Y
1Y
2Y
GND = 7
V
CC
= 14
TRUTH TABLE
Pinout
A
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 V
CC
13 4A
12 4B
11 4Y
10 3A
9 3B
8 3Y
INPUTS
B
L
L
H
H
OUTPUTS
Y
H
H
H
L
L
H
L
H
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1998
File Number
3876.1
1

CD54AC00 Related Products

CD54AC00 54AC00 CD54AC00F3A CD54ACT00F3A
Description AC SERIES, QUAD 2-INPUT NAND GATE, CDIP14 AC SERIES, QUAD 2-INPUT NAND GATE, CDIP14 AC SERIES, QUAD 2-INPUT NAND GATE, CDIP14 ACT SERIES, QUAD 2-INPUT NAND GATE, CDIP14
Number of functions 4 4 4 4
Number of terminals 14 14 14 14
Minimum operating temperature -55 Cel -55 Cel -55 Cel -55 Cel
Maximum operating temperature 125 Cel 125 Cel 125 Cel 125 Cel
Rated supply voltage 3.3 3.3 3.3 5 V
Minimum supply/operating voltage 1.5 V 1.5 V 1.5 V 4.5 V
Maximum supply/operating voltage 5.5 V 5.5 V 5.5 V 5.5 V
state Active Active Active DISCONTINUED
Logic IC type NAND GATE NAND GATE NAND GATE NAND gate
series AC AC AC ACT
Number of inputs 2 2 2 2
Packaging Materials CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED Ceramic, Glass-SEALED
packaging shape RECTANGULAR RECTANGULAR RECTANGULAR Rectangle
Package Size IN-LINE IN-LINE IN-LINE IN-line
propagation delay TPD 91 ns 91 ns 91 ns 13.2 ns
Craftsmanship CMOS CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY MILITARY
Terminal form THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-hole
Terminal location DUAL DUAL DUAL pair
Processing package description CERAMIC, DIP-14 CERAMIC, DIP-14 CERAMIC, DIP-14 -
each_compli Yes Yes Yes -
sub_category Gates Gates Gates -
jesd_30_code R-GDIP-T14 R-GDIP-T14 R-GDIP-T14 -
load_capacitance__cl_ 50 pF 50 pF 50 pF -
max_i_ol_ 0.0240 Am 0.0240 Am 0.0240 Am -
moisture_sensitivity_level NOT APPLICABLE NOT APPLICABLE NOT APPLICABLE -
ckage_code DIP DIP DIP -
ckage_equivalence_code DIP14,.3 DIP14,.3 DIP14,.3 -
cking_method TUBE TUBE TUBE -
eak_reflow_temperature__cel_ NOT APPLICABLE NOT APPLICABLE NOT APPLICABLE -
wer_supplies__v_ 3.3/5 3.3/5 3.3/5 -
._delay_nom_su 10.2 ns 10.2 ns 10.2 ns -
qualification_status COMMERCIAL COMMERCIAL COMMERCIAL -
schmitt_trigge NO NO NO -
screening_level 38535Q/M;38534H;883B 38535Q/M;38534H;883B 38535Q/M;38534H;883B -
seated_height_max 5.08 mm 5.08 mm 5.08 mm -
surface mount NO NO NO -
terminal coating NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED -
Terminal spacing 2.54 mm 2.54 mm 2.54 mm -
ime_peak_reflow_temperature_max__s_ NOT APPLICABLE NOT APPLICABLE NOT APPLICABLE -
length 19.43 mm 19.43 mm 19.43 mm -
width 7.62 mm 7.62 mm 7.62 mm -
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