Features
•
3.0V to 5.5V Operation
•
Industry Standard Architecture
•
•
•
•
•
– Emulates Many 20-Pin PALs
®
– Low Cost Easy-to-Use Software Tools
High Speed
– 10 ns Maximum Pin-to-Pin Delay
Ultra-Low Power
– 5
µ
A (Max.) Pin-Controlled Power Down Mode Option
– Typical 100 nA Standby
CMOS and TTL Compatible Inputs and Outputs
– I/O Pin Keeper Circuits
Advanced Flash Technology
– Reprogrammable
– 100% Tested
High Reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-Line and Surface Mount Packages in Standard Pinouts
High-
Performance
EE PLD
ATF16LV8C
•
•
Description
The ATF16LV8C is a high-performance EECMOS Programmable Logic Device that
utilizes Atmel's proven electrically erasable Flash memory technology. Speeds down
to 10 ns and a 5
µA
pin-controlled power down mode option are offered. All speed
ranges are specified over the full 3.0V to 5.25V range for industrial and commercial
temperature ranges.
(continued)
Pin Configurations
Pin Name
CLK
I
I/O
OE
VCC
PD
Function
Clock
Logic Inputs
Bidirectional Buffers
Output Enable
(+3V to 5.5V) Supply
Programmable Power
Down Option
PLCC
I/CLK
I1
I2
PD/I3
I4
I5
I6
I7
I8
GND
1
2
3
4
5
6
7
8
9
10
TSSOP
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
19/OE
DIP/SOIC
Rev. 0403E–06/98
Top View
1
The ATF16LV8C incorporates a superset of the generic
architectures, which allows direct replacement of the 16R8
family and most 20-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
modes of operation, configured automatically with soft-
ware, allow highly complex logic functions to be realized.
The ATF16LV8C can significantly reduce total system
power, thereby enhancing system reliability and reducing
power supply costs. When pin 4 is configured as the power
down control pin, supply current drops to less than 5
µA
whenever the pin is high. If the power down feature isn't
required for a particular application, pin 4 may be used as a
logic input. Also, the pin keeper circuits eliminate the need
for internal pull-up resistors along with their attendant
power consumption.
Block Diagram
Note:
1.
Includes optional PD control pin.
Absolute Maximum Ratings*
Temperature Under Bias .................................. -40°C to +85°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
(1)
Note:
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
1.
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Minimum voltage is -0.6V dc, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is Vcc + 0.75V dc, which
may overshoot to 7.0V for pulses of less than 20
ns.
DC and AC Operating Conditions
Commercial
Operating Temperature (Case)
V
CC
Power Supply
0°C - 70°C
3.0V to 5.5V
2
ATF16LV8C
ATF16LV8C
DC Characteristics
Symbol
I
IL
I
IH
I
CC1
(1)
Parameter
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
Power Supply Current
Condition
0
≤
V
IN
≤
V
IL
(MAX)
1.8
≤
V
IN
≤
V
CC
15 MHz, V
CC
= MAX,
V
IN
= 0, V
CC,
Outputs Open
V
CC
= MAX,
V
IN
= 0, V
CC
V
OUT
= 0.5V;
V
CC
= 3V; T
A
= 25°C
MIN < V
CC
< MAX
Min
Typ
Max
-10
10
55
Units
µA
µA
mA
I
PD(1)
I
OS
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
Note:
Power Supply Current, Power Down Mode
Output Short Circuit Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
1. All I
CC
parameters measured with outputs open.
0.1
5
-150
µA
mA
V
V
V
V
mA
mA
-0.5
2.0
0.8
V
CC
+ 1
0.5
V
CC
= MIN; All Outputs
I
OL
= 8 mA
V
CC
= MIN
I
OL
= -500 mA
V
CC
= MIN
V
CC
= MIN
2.4
8
-4
AC Waveforms
(1)
Note:
1.
Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
3
AC Characteristics
-10
Symbol
t
PD
t
CF
t
CO
t
S
t
H
t
P
t
W
Parameter
Input or Feedback to Non-Registered Output
Clock to Feedback
Clock to Output
Input or Feedback Setup Time
Input Hold Time
Clock Period
Clock Width
External Feedback 1/(t
S
+ t
CO
)
F
MAX
Internal Feedback 1/(t
S
+ t
CF
)
No Feedback 1/(t
P
)
t
EA
t
ER
t
PZX
t
PXZ
Input to Output Enable —
Product Term
Input to Output Disable —
Product Term
OE pin to Output Enable
OE pin to Output Disable
3
2
2
1.5
2
7
0
12
6
71.4
83.3
83.3
10
10
8
8
3
2
2
1.5
Min
1
Max
10
5
7
2
12
0
16
8
45.5
50
62.5
15
15
15
15
Min
1
-15
Max
15
8
10
Units
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
Power Down AC Characteristics
(1)(2)(3)
-10
Symbol
t
IVDH
t
GVDH
t
CVDH
t
DHIX
t
DHGX
t
DHCX
t
DLIV
t
DLGV
t
DLCV
t
DLOV
Notes:
Parameter
Valid Input Before PD High
Valid OE Before PD High
Valid Clock Before PD High
Input Don't Care After PD High
OE Don't Care After PD High
Clock Don't Care After PD High
PD Low to Valid Input
PD Low to Valid OE
PD Low to Valid Clock
PD Low to Valid Output
1. Output data is latched and held.
2. HI-Z outputs remain HI-Z.
3. Clock and input transitions are ignored.
Min
10
0
0
10
10
10
10
25
25
30
Max
Min
15
0
0
15
15
15
15
30
30
35
-15
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
ATF16LV8C
ATF16LV8C
Input Test Waveforms and
Measurement Levels:
Output Test Loads:
Commercial
3.3V
R1 = 316
OUTPUT
PIN
t
R
, t
F
< 1.5ns (10% to 90%)
R2 = 348
CL = 35 pF
Note:
Similar devices are tested with slightly different loads.
These load differences may affect output signals’ delay
and slew rate. Atmel devices are tested with sufficient
margins to meet compatible devices.
Pin Capacitance
(1)
(f = 1 MHz, T = 25°C)
Typ
C
IN
C
OUT
Note:
5
6
Max
8
8
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The ATF16LV8C’s registers are designed to reset during
power up. At a point delayed slightly from V
CC
crossing
V
RST
, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
CC
actually rises in the system, the fol-
lowing conditions are required:
1. The V
CC
rise must be monotonic from below 0.7
volts.
2. The signals from which the clock is derived must
remain stable during T
PR
.
3. After T
PR
, all input and feedback setup times must
be met before driving the clock term high.
Parameter
T
PR
Description
Power-Up
Reset Time
Power-Up
Reset
Voltage
Typ
600
Max
1,000
Units
ns
V
RST
2.5
3.0
V
5
Analogue and Mixed Signal
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