PRELIMINARY
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷2/4,÷4/5/6,
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
G
ENERATOR
F
EATURES
•
2 divide by 2/4 differential 3.3V LVPECL outputs;
2 divide by 4/5/6 differential 3.3V LVPECL outputs
•
1 differential CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Input frequency: >1GHz (typical)
•
Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
•
Output skew: 38ps (maximum)
•
Part-to-part skew: 375ps (maximum)
•
Bank skew: Bank A - TBD,
Bank B - TBD
•
Propagation delay: 2.1ns (maximum)
•
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.6V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3V to -3.6V
•
-40°C to 85°C ambient operating temperature
•
Compatible with MC10EP139, MC100EP139
ICS87339-11
G
ENERAL
D
ESCRIPTION
The ICS87339-11 is a low skew, high perfor-
mance Differential-to-3.3V LVPECL / ECL Clock
HiPerClockS™
Generator/Divider and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS87339-11 has one
differential clock input pair. The CLK, nCLK pair can accept
most standard differential input levels. The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS87339-11 ideal for clock distribution applications
demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
DIV_SELA
QA0
nQA0
nCLK_EN
D
Q
LE
CLK
nCLK
÷2, ÷4
P
IN
A
SSIGNMENT
V
CC
nCLK_EN
DIV_SELB0
CLK
nCLK
nc
MR
V
CC
DIV_SELB1
DIV_SELA
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
V
EE
R
QA1
nQA1
QB0
nQB0
÷4, ÷5, ÷6
ICS87339-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
20-Lead SOIC
7.5mm x 12.8mm x 2.25mm package body
M Package
Top View
R
QB1
nQB1
MR
DIV_SELB0
DIV_SELB1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87339AG-11
www.icst.com/products/hiperclocks.html
REV. A MAY 15, 2003
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷2/4,÷4/5/6,
D
IFFERENTIAL
-
TO
-3.3
V
LVPECL / ECL C
LOCK
G
ENERATOR
Type
Description
Positive supply pins.
Pulldown Clock enable. LVCMOS / LVTTL interface levels.
Selects divide value for Bank B outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
No connect.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inver ted outputs nQx to go
Pulldown
high. When logic LOW, the internal dividers are the outputs are enabled.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank B outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Selects divide value for Bank A outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
internal input resistors. See Table 2, Pin Characteristics, for typical values.
Pullup
ICS87339-11
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 8, 20
2
3
4
5
6
7
Name
V
CC
nCLK_EN
DIV_SELB0
CLK
nCLK
nc
MR
Power
Input
Input
Input
Input
Unused
Input
9
10
DIV_SELB1
DIV_SELA
Input
Input
Power
11
V
EE
12, 13
nQB1, QB1 Output
14, 15
nQB0, QB0 Output
16, 17
nQA1, QA1 Output
18, 19
nQA0, QA0 Output
NOTE:
Pullup
and
Pulldown
refer to
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
MR
1
0
0
0
0
0
0
0
0
0
87339AG-11
Outputs
DIV_SELB1
X
X
0
1
0
1
0
1
0
1
QA0, QA1
LOW
Not
Switching
÷2
÷2
÷2
÷2
÷4
÷4
÷4
÷4
nQA0, nQA1
HIGH
Not
Switching
÷2
÷2
÷2
÷2
÷4
÷4
÷4
÷4
QB0, QB1
LOW
Not
Switching
÷4
÷5
÷6
÷5
÷4
÷5
÷6
÷5
nQB0, nQB1
HIGH
Not
Switching
÷4
÷5
÷6
÷5
÷4
÷5
÷6
÷5
REV. A MAY 15, 2003
nCLK_EN
X
1
0
0
0
0
0
0
0
0
DIV_SELA
X
X
0
0
0
0
1
1
1
1
DIV_SELB0
X
X
0
0
1
1
0
0
1
1
NOTE: After nCLK_EN switches, the clock outputs stop switching following a rising and falling input clock edge.
www.icst.com/products/hiperclocks.html
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷2/4,÷4/5/6,
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
G
ENERATOR
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
ICS87339-11
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
85
Maximum
3.6
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
nCLK_EN, MR,
DIV_SELA, DIV_SELBx
nCLK_EN, MR,
DIV_SELA, DIV_SELBx
V
IN
= V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
IN
= V
CC
= 3.6V
V
IN
= V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
V
IN
= 0V, V
CC
= 3.6V
-150
-5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
V
EE
+ 0.5
NOTE 1, 2
NOTE 1: For single ended applications
,
the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
87339AG-11
www.icst.com/products/hiperclocks.html
3
REV. A MAY 15, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷2/4,÷4/5/6,
D
IFFERENTIAL
-
TO
-3.3
V
LVPECL / ECL C
LOCK
G
ENERATOR
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 1.0
V
CC
- 1.7
1.0
Units
V
V
V
ICS87339-11
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
t
PD
Input Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Bank Skew; NOTE 3, 5
Bank A
Bank B
TB D
TB D
375
600
CLK to Q (Diff)
1.65
Test Conditions
Minimum
Typical
>1
2.1
38
Maximum
Units
GHz
ns
ps
ps
ps
ps
ps
t
sk(o)
t
sk(b)
t
sk(pp)
Par t-to-Par t Skew; NOTE 4, 5
t
R
/ t
F
Output Rise/Fall Time
20% to 80%
200
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points
NOTE 3: Defined as skew within a bank of outputs and with equal load conditions.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
87339AG-11
www.icst.com/products/hiperclocks.html
4
REV. A MAY 15, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷2/4,÷4/5/6,
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
G
ENERATOR
ICS87339-11
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
CC
, V
CCO
= 2V
V
CC
Qx
SCOPE
nCLK
V
Cross Points
V
LVPECL
nQx
PP
CMR
CLK
V
EE
V
EE
= -1.3V ± 0.3V
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
nQx
Qx
nQy
Qy
tsk(o)
PART 1
nQx
Qx
PART 2
nQy
Qy
tsk(pp)
O
UTPUT
S
KEW
nCLK
P
ART
-
TO
-P
ART
S
KEW
80%
80%
V
SW I N G
CLK
20%
20%
t
R
nQAx,
nQBx
QAx,
QBx
Clock Outputs
t
F
t
PD
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
87339AG-11
www.icst.com/products/hiperclocks.html
5
REV. A MAY 15, 2003
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