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ICS87339AG-11LF

Description
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20
Categorylogic    logic   
File Size151KB,13 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Environmental Compliance
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ICS87339AG-11LF Overview

Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20

ICS87339AG-11LF Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerRenesas Electronics Corporation
package instructionTSSOP,
Reach Compliance Codecompli
Other featuresECL MODE; VCC=0 WITH VEE=-3V TO -3.6V
Input adjustmentDIFFERENTIAL
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length6.5 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals20
Actual output times4
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)2.1 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.038 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
PRELIMINARY
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷2/4,÷4/5/6,
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
G
ENERATOR
F
EATURES
2 divide by 2/4 differential 3.3V LVPECL outputs;
2 divide by 4/5/6 differential 3.3V LVPECL outputs
1 differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Input frequency: >1GHz (typical)
Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
Output skew: 38ps (maximum)
Part-to-part skew: 375ps (maximum)
Bank skew: Bank A - TBD,
Bank B - TBD
Propagation delay: 2.1ns (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.6V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3V to -3.6V
-40°C to 85°C ambient operating temperature
Compatible with MC10EP139, MC100EP139
ICS87339-11
G
ENERAL
D
ESCRIPTION
The ICS87339-11 is a low skew, high perfor-
mance Differential-to-3.3V LVPECL / ECL Clock
HiPerClockS™
Generator/Divider and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS87339-11 has one
differential clock input pair. The CLK, nCLK pair can accept
most standard differential input levels. The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS87339-11 ideal for clock distribution applications
demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
DIV_SELA
QA0
nQA0
nCLK_EN
D
Q
LE
CLK
nCLK
÷2, ÷4
P
IN
A
SSIGNMENT
V
CC
nCLK_EN
DIV_SELB0
CLK
nCLK
nc
MR
V
CC
DIV_SELB1
DIV_SELA
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
V
EE
R
QA1
nQA1
QB0
nQB0
÷4, ÷5, ÷6
ICS87339-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
20-Lead SOIC
7.5mm x 12.8mm x 2.25mm package body
M Package
Top View
R
QB1
nQB1
MR
DIV_SELB0
DIV_SELB1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87339AG-11
www.icst.com/products/hiperclocks.html
REV. A MAY 15, 2003
1

ICS87339AG-11LF Related Products

ICS87339AG-11LF ICS87339AG-11
Description Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20 Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20
Is it Rohs certified? conform to incompatible
Maker Renesas Electronics Corporation Renesas Electronics Corporation
package instruction TSSOP, TSSOP,
Reach Compliance Code compli compli
Other features ECL MODE; VCC=0 WITH VEE=-3V TO -3.6V ECL MODE; VCC=0 WITH VEE=-3V TO -3.6V
Input adjustment DIFFERENTIAL DIFFERENTIAL
JESD-30 code R-PDSO-G20 R-PDSO-G20
JESD-609 code e3 e0
length 6.5 mm 6.5 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Number of functions 1 1
Number of terminals 20 20
Actual output times 4 4
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 240
propagation delay (tpd) 2.1 ns 2.1 ns
Certification status Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.038 ns 0.038 ns
Maximum seat height 1.2 mm 1.2 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3 V 3 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Tin/Lead (Sn/Pb)
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 20
width 4.4 mm 4.4 mm
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