L3L1ZC473MAB3S datasheet, PDF - EEWORLD Datasheet

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L3L1ZC473MAB3S: DescriptionCeramic Capacitor, Multilayer, Ceramic, 10V, 20% +Tol, 20% -Tol, X7R, 15% TC, 0.047uF, Surface Mount, 0612, CHIP; CategoryPassive components capacitor; File Size158KB，4 Pages; ManufacturerAVX

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L3L1ZC473MAB3S Overview

Ceramic Capacitor, Multilayer, Ceramic, 10V, 20% +Tol, 20% -Tol, X7R, 15% TC, 0.047uF, Surface Mount, 0612, CHIP

L3L1ZC473MAB3S Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	AVX
package instruction	, 0612
Reach Compliance Code	_compli
ECCN code	EAR99
capacitance	0.047 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	0.55 mm
JESD-609 code	e0
length	3.2 mm
Manufacturer's serial number	L3
Installation features	SURFACE MOUNT
multi-layer	Yes
negative tolerance	20%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package shape	RECTANGULAR PACKAGE
Package form	SMT
method of packing	TR, 13 INCH
positive tolerance	20%
Rated (DC) voltage (URdc)	10 V
series	L
size code	0612
surface mount	YES
Temperature characteristic code	X7R
Temperature Coefficient	15% ppm/°C
Terminal surface	Tin/Lead (Sn/Pb)
Terminal shape	WRAPAROUND
width	1.6 mm

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Low Inductance Capacitors

Introduction

The signal integrity characteristics of a Power Delivery

Network (PDN) are becoming critical aspects of board level

and semiconductor package designs due to higher operating

frequencies, larger power demands, and the ever shrinking

lower and upper voltage limits around low operating voltages.

These power system challenges are coming from mainstream

designs with operating frequencies of 300MHz or greater,

modest ICs with power demand of 15 watts or more, and

operating voltages below 3 volts.

The classic PDN topology is comprised of a series of

capacitor stages. Figure 1 is an example of this architecture

with multiple capacitor stages.

An ideal capacitor can transfer all its stored energy to a load

instantly. A real capacitor has parasitics that prevent

instantaneous transfer of a capacitor’s stored energy. The

true nature of a capacitor can be modeled as an RLC

equivalent circuit. For most simulation purposes, it is possible

to model the characteristics of a real capacitor with one

Slowest Capacitors

capacitor, one resistor, and one inductor. The RLC values in

this model are commonly referred to as equivalent series

capacitance (ESC), equivalent series resistance (ESR), and

equivalent series inductance (ESL).

The ESL of a capacitor determines the speed of energy

transfer to a load. The lower the ESL of a capacitor, the faster

that energy can be transferred to a load. Historically, there

has been a tradeoff between energy storage (capacitance)

and inductance (speed of energy delivery). Low ESL devices

typically have low capacitance. Likewise, higher capacitance

devices typically have higher ESLs. This tradeoff between

ESL (speed of energy delivery) and capacitance (energy

storage) drives the PDN design topology that places the

fastest low ESL capacitors as close to the load as possible.

Low Inductance MLCCs are found on semiconductor

packages and on boards as close as possible to the load.

Fastest Capacitors

Semiconductor Product

Bulk

Board-Level

Package-Level

Die-Level

Low Inductance Decoupling Capacitors

Figure 1 Classic Power Delivery Network (PDN) Architecture

LOW INDUCTANCE CHIP CAPACITORS

The key physical characteristic determining equivalent series

inductance (ESL) of a capacitor is the size of the current loop

it creates. The smaller the current loop, the lower the ESL. A

standard surface mount MLCC is rectangular in shape with

electrical terminations on its shorter sides. A Low Inductance

Chip Capacitor (LICC) sometimes referred to as Reverse

Geometry Capacitor (RGC) has its terminations on the longer

side of its rectangular shape.

When the distance between terminations is reduced, the size

of the current loop is reduced. Since the size of the current

loop is the primary driver of inductance, an 0306 with a

smaller current loop has significantly lower ESL then an 0603.

The reduction in ESL varies by EIA size, however, ESL is

typically reduced 60% or more with an LICC versus a

standard MLCC.

INTERDIGITATED CAPACITORS

The size of a current loop has the greatest impact on the ESL

characteristics of a surface mount capacitor. There is a

secondary method for decreasing the ESL of a capacitor.

This secondary method uses adjacent opposing current

loops to reduce ESL. The InterDigitated Capacitor (IDC)

utilizes both primary and secondary methods of reducing

inductance. The IDC architecture shrinks the distance

between terminations to minimize the current loop size, then

further reduces inductance by creating adjacent opposing

current loops.

An IDC is one single capacitor with an internal structure that

has been optimized for low ESL. Similar to standard MLCC

versus LICCs, the reduction in ESL varies by EIA case size.

Typically, for the same EIA size, an IDC delivers an ESL that

is at least 80% lower than an MLCC.

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