Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5644A
Rev. 7, Jan 2012
MPC5644A
MPC5644A Microcontroller
Data Sheet
176 (24 x 24 mm)
208 (17 x 17 mm)
324 (23 x 23 mm)
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150 MHz e200z4 Power Architecture core
— Variable length instruction encoding (VLE)
— Superscalar architecture with 2 execution units
— Up to 2 integer or floating point instructions per cycle
— Up to 4 multiply and accumulate operations per cycle
Memory organization
— 4 MB on-chip flash memory with ECC and Read
While Write (RWW)
— 192 KB on-chip SRAM with standby functionality
(32 KB) and ECC
— 8 KB instruction cache (with line locking),
configurable as 2- or 4-way
— 14 + 3 KB eTPU code and data RAM
— 5
4 crossbar switch (XBAR)
— 24-entry MMU
— External Bus Interface (EBI) with slave and master
port
Fail Safe Protection
— 16-entry Memory Protection Unit (MPU)
— CRC unit with 3 sub-modules
— Junction temperature sensor
Interrupts
— Configurable interrupt controller (with NMI)
— 64-channel DMA
Serial channels
— 3
eSCI
— 3
DSPI (2 of which support downstream Micro
Second Channel [MSC])
— 3
FlexCAN with 64 messages each
— 1
FlexRay module (V2.1) up to 10 Mbit/s with dual
or single channel and 128 message objects and ECC
1
eMIOS: 24 unified channels
1
eTPU2 (second generation eTPU)
— 32 standard channels
— 1
reaction module (6 channels with three outputs
per channel)
2 enhanced queued analog-to-digital converters
(eQADCs)
— Forty 12-bit input channels (multiplexed on 2 ADCs);
expandable to 56 channels with external multiplexers
— 6 command queues
— Trigger and DMA support
— 688 ns minimum conversion time
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On-chip CAN/SCI/FlexRay Bootstrap loader with Boot
Assist Module (BAM)
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Nexus
— Class 3+ for the e200z4 core
— Class 1 for the eTPU
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JTAG (5-pin)
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Development Trigger Semaphore (DTS)
— Register of semaphores (32-bits) and an identification
register
— Used as part of a triggered data acquisition protocol
— EVTO pin is used to communicate to the external tool
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Clock generation
— On-chip 4–40 MHz main oscillator
— On-chip FMPLL (frequency-modulated phase-locked
loop)
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Up to 120 general purpose I/O lines
— Individually programmable as input, output or special
function
— Programmable threshold (hysteresis)
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Power reduction mode: slow, stop and stand-by modes
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Flexible supply scheme
— 5 V single supply with external ballast
— Multiple external supply: 5 V, 3.3 V and 1.2 V
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Packages
— 176 LQFP
— 208 MAPBGA
— 324 TEPBGA
496-pin CSP (calibration tool only)
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This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009–2012. All rights reserved.
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.4 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.4.1 e200z4 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.4.2 Crossbar Switch (XBAR) . . . . . . . . . . . . . . . . . . .6
1.4.3 eDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.4.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . .7
1.4.5 Memory protection unit (MPU). . . . . . . . . . . . . . .8
1.4.6 FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.4.7 SIU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.4.8 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.4.9 BAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.4.10 eMIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4.11 eTPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4.12 Reaction module . . . . . . . . . . . . . . . . . . . . . . . .13
1.4.13 eQADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.4.14 DSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.4.15 eSCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.4.16 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.4.17 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4.18 System timers . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.4.19 Software watchdog timer (SWT) . . . . . . . . . . . .17
1.4.20 Cyclic redundancy check (CRC) module . . . . . .18
1.4.21 Error correction status module (ECSM). . . . . . .18
1.4.22 External bus interface (EBI). . . . . . . . . . . . . . . .18
1.4.23 Calibration EBI. . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4.24 Power management controller (PMC) . . . . . . . .19
1.4.25 Nexus port controller . . . . . . . . . . . . . . . . . . . . .19
1.4.26 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4.27 Development Trigger Semaphore (DTS) . . . . . .20
1.5 MPC5644A series architecture . . . . . . . . . . . . . . . . . . .20
1.5.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.2 Block summary . . . . . . . . . . . . . . . . . . . . . . . . .22
Pinout and signal description . . . . . . . . . . . . . . . . . . . . . . . . .24
2.1 176 LQFP pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.2 208 MAP BGA ballmap . . . . . . . . . . . . . . . . . . . . . . . . .26
2.3 324 TEPBGA ballmap. . . . . . . . . . . . . . . . . . . . . . . . . .27
2.4 Signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.5 Signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .65
3.2 Maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3.1 General notes for specifications at maximum
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.4 EMI (electromagnetic interference) characteristics . . . 71
3.5 Electrostatic discharge (ESD) characteristics . . . . . . . 71
3.6 Power management control (PMC) and power on reset
(POR) electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 72
3.6.1 Voltage regulator controller (VRC)
electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 75
3.6.2 Regulator Example. . . . . . . . . . . . . . . . . . . . . . 76
3.6.3 Recommended power transistors . . . . . . . . . . 77
3.7 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . 77
3.8 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . 78
3.9 I/O pad current specifications . . . . . . . . . . . . . . . . . . . 85
3.9.1 I/O pad V
RC33
current specifications . . . . . . . . 86
3.9.2 LVDS pad specifications. . . . . . . . . . . . . . . . . . 87
3.10 Oscillator and PLLMRFM electrical characteristics . . . 88
3.11 Temperature sensor electrical characteristics . . . . . . . 90
3.12 eQADC electrical characteristics . . . . . . . . . . . . . . . . . 90
3.13 Configuring SRAM wait states . . . . . . . . . . . . . . . . . . . 93
3.14 Platform flash controller electrical characteristics . . . . 93
3.15 Flash memory electrical characteristics. . . . . . . . . . . . 93
3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.16.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . 95
3.17 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.17.1 Reset and configuration pin timing . . . . . . . . . . 98
3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 99
3.17.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.17.4 External Bus Interface (EBI) and calibration
bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.17.5 External interrupt timing (IRQ pin) . . . . . . . . . 110
3.17.6 eTPU timing . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.17.7 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . .111
3.17.8 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . .111
3.17.9 eQADC SSI timing . . . . . . . . . . . . . . . . . . . . . 118
3.17.10FlexCAN system clock source. . . . . . . . . . . . 119
Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 120
4.1.1 176 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.1.2 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . 123
4.1.3 324 TEPBGA . . . . . . . . . . . . . . . . . . . . . . . . . 125
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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MPC5644A Microcontroller Data Sheet, Rev. 7
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