TC59LM814/06CFT-50,-55,-60
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
4,194,304-WORDS
×
4 BANKS
×
16-BITS Network FCRAM
TM
8,388,608-WORDS
×
4 BANKS
×
8-BITS Network FCRAM
DESCRIPTION
TM
Network FCRAM
TM
is Double Data Rate Fast Cycle Random Access Memory. TC59LM814/06CFT are Network
FCRAM
TM
containing 268,435,456 memory cells. TC59LM814CFT is organized as 4,194,304-words
×
4 banks s× 16
bits, TC59LM806CFT is organized as 8,388,608 words
×
4 banks
×
8 bits. TC59LM814/06CFT feature a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. TC59LM814/06CFT can operate fast core cycle
using the FCRAM
TM
core architecture compared with regular DDR SDRAM.
TC59LM814/06CFT is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAM
TM
is capable of high quality fast data
transfer under light loading condition.
FEATURES
PARAMETER
CL
=
3
CL
=
4
t
RC
Random Read/Write Cycle Time (min)
t
RAC
Random Access Time (max)
I
DD1S
Operating Current (single bank) (max)
l
DD2P
Power Down Current (max)
l
DD6
Self-Refresh Current (max)
t
CK
Clock Cycle Time (min)
-50
5.5 ns
5 ns
25 ns
22 ns
190 mA
2 mA
3 mA
TC59LM814/06
-55
6 ns
5.5 ns
27.5 ns
24 ns
180 mA
2 mA
3 mA
-60
6.5 ns
6 ns
30 ns
26 ns
170 mA
2 mA
3 mA
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully Synchronous Operation
•
Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
•
Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 5 ns minimum
Clock: 200 MHz maximum
Data: 400 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Bidirectional Data Strobe Signal
Distributed Auto-Refresh cycle in 7.8
µs
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency
=
CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency
=
3, 4
Burst Length
=
2, 4
Organization
TC59LM814CFT: 4,194,304 words
×
4 banks
×
16 bits
TC59LM806CFT: 8,388,608 words
×
4 banks
×
8 bits
Power Supply Voltage V
DD
:
2.5 V
±
0.15 V
V
DDQ
: 2.5 V
±
0.15 V
2.5 V CMOS I/O comply with SSTL-2 (half strength driver)
Package:
400
×
875 mil, 66 pin TSOPII, 0.65 mm pin pitch (TSOPII66-P-400-0.65)
Notice: FCRAM is a trademark of Fujitsu Limited, Japan.
2002-08-19
1/38
TC59LM814/06CFT-50,-55,-60
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
DDQ
V
IN
V
OUT
V
REF
T
opr
T
stg
T
solder
P
D
I
OUT
PARAMETER
Power Supply Voltage
Power Supply Voltage (for I/O buffer)
Input Voltage
DQ pin Voltage
Input Reference Voltage
Operating Temperature
Storage Temperature
Soldering Temperature (10 s)
Power Dissipation
Short Circuit Output Current
RATING
−0.3~
3.3
−0.3~V
DD
+
0.3
−0.3~V
DD
+
0.3
−0.3~V
DDQ
+
0.3
−0.3~3.3
0~70
−55~150
260
1
±50
UNIT
V
V
V
V
V
°C
°C
°C
W
mA
NOTES
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS
(Notes: 1)(Ta
=
0°~70°C)
SYMBOL
V
DD
V
DDQ
V
REF
V
IH
(DC)
V
IL
(DC)
V
ICK
(DC)
V
ID
(DC)
V
IH
(AC)
V
IL
(AC)
V
ID
(AC)
V
X
(AC)
V
ISO
(AC)
PARAMETER
Power Supply Voltage
Power Supply Voltage (for I/O buffer)
Input Reference Voltage
Input DC High Voltage
Input DC Low Voltage
Differential Clock DC Input Voltage
Input Differential Voltage.
CLK and
CLK
inputs (DC)
Input AC High Voltage
Input AC Low Voltage
Input Differential Voltage.
CLK and
CLK
inputs (AC)
Differential AC Input Cross Point Voltage
Differential Clock AC Middle Level
MIN
2.35
2.35
V
DDQ
/2
×
96%
V
REF
+
0.2
−0.1
−0.1
0.4
V
REF
+
0.35
−0.1
0.7
V
DDQ
/2
−
0.2
V
DDQ
/2
−
0.2
TYP.
2.5
V
DD
V
DDQ
/2
MAX
2.65
V
DD
V
DDQ
/2
×
104%
V
DDQ
+
0.2
V
REF
−
0.2
V
DDQ
+
0.1
V
DDQ
+
0.2
V
DDQ
+
0.2
V
REF
−
0.35
V
DDQ
+
0.2
V
DDQ
/2
+
0.2
V
DDQ
/2
+
0.2
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
2
5
5
10
7, 10
3, 6
4, 6
7, 10
8, 10
9, 10
NOTES
2002-08-19
4/38
TC59LM814/06CFT-50,-55,-60
Note:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
All voltages referenced to V
SS
, V
SSQ
.
V
REF
is expected to track variations in V
DDQ
DC level of the transmitting device.
Peak to peak AC noise on V
REF
may not exceed
±2%
V
REF
(DC).
Overshoot limit: V
IH (max)
=
V
DDQ
+
0.9 V with a pulse width
≤
5 ns.
Undershoot limit: V
IL (min)
= −0.9
V with a pulse width
≤
5 ns.
V
IH
(DC) and V
IL
(DC) are levels to maintain the current logic state.
V
IH
(AC) and V
IL
(AC) are levels to change to the new logic state.
V
ID
is magnitude of the difference between CLK input level and CLK input level.
The value of V
X
(AC) is expected to equal V
DDQ
/2 of the transmitting device.
V
ISO
means {V
ICK
(CLK)
+
V
ICK
( CLK )} /2
Refer to the figure below.
CLK
V
x
CLK
V
x
V
ICK
V
x
V
x
V
ICK
V
x
V
ICK
V
ID
(AC)
V
ICK
V
SS
|V
ID
(AC)|
0 V Differential
V
ISO
V
ISO
(min)
V
SS
V
ISO
(max)
(11)
In the case of external termination, VTT (termination voltage) should be gone in the range of V
REF
(DC)
±
0.04 V.
CAPACITANCE
(V
DD
,
V
DDQ
=
2.5 V, f
=
1 MHz, Ta
=
25°C)
SYMBOL
C
IN
C
INC
C
I/O
C
NC
C
NC
1
2
PARAMETER
Input pin Capacitance
Clock pin (CLK,
CLK
) Capacitance
I/O pin (DQ, DQS) Capacitance
NC pin Capacitance
NC pin Capacitance
2
1
MIN
2.5
2.5
4.0
4.0
MAX
4.0
4.0
6.0
1.5
6.0
UNIT
pF
pF
pF
pF
pF
Note: These parameters are periodically sampled and not 100% tested.
2
The NC pins have additional capacitance for adjustment of the adjacent pin capacitance.
2
The NC pins have Power and Ground clamp.
2002-08-19
5/38
京公网安备 11010802033920号
EEWORLD
