TOSHIBA MOS MEMORY PRODUCTS
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
DESCRIPTION
The TC5565APL/AFL is 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology, and
operates from a single 5V supply. Advanced circuit techniques provide both high speed and low power features with a maximum
operating current of 5mA/MHz and maximum access time of 100ns/120ns/150ns.
When CE2 is a logical low or \CEl is a logical high, the device is placed in low power standby mode in which standby current is 2uA
typically. The TC5565APL/AFL has three control inputs. Two chip enable (\CE1, CE2) allow for device selection and data retention
control, and an output enable input
(\OE)
provides fast memory access. Thus the TC5565APL/AFL is suitable for use in various
microprocessor application systems where high speed, low power, and battery back up are required.
The TC5565APL also features pin compatibility with the 64K bit EPROM (TMM2764D).
RAM and EPROM are then interchangeable in the same socket,
resulting
in flexibility in the definition of the quantity of RAM versus
EPROM in microprocessor application systems. The TC5565APL is offered in a dual-in-line 28 pin standard plastic package. The
TC5565AFL is offered in 28 pin mini Flat Package.
FEATURES
Low Power Dissipation
27.5mW/MHz(Max.) operating
•
Standby Current: 100uA(Max.) Ta=70°C
•
Access Time
TC5565APL/AFL-10 : 100ns(Max.)
TC5565APL/AFL-12 : 120ns(Max.)
TC5565APL/AFL-15 : 150ns(Max.)
•
5V Single Power Supply
-
•
Power Down Features: CE2, \CE1
•
Fully Static Operation
Data Retention Supply Voltage: 2.0-5.5V
•
•
•
•
Directly TTL Compatible
: All
Inputs and Outputs
Pin Compatible with 2764 type EPROM
TC5565APL Family (Package Type)
Package Type
Device Name
600 mil DIP
TC5565APL
300 mil DIP
*TC5563APL
(Slim Package)
Flat Package
TC5565AFL
(SOP)
* See TC5563APL Technical Data.
BLOCK DIAGRAM
PIN CONNECTION
(TOP VIEW)
AO-A12
R/W
\OE
\CE1, CE2
I/O1 – I/O8
V
DD
GND
N.C.
Address Inputs
Read/Write Control Input
Output Enable Input
Chip Enable Inputs
Data Input/Output
Power (+5V)
Ground
No Connection
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
OPERATION MODE
\CE1
CE2
\OE
R/W
1/01-T/08
POWER
Read
Write
Output Deselect
Standby
L
L
L
H
H
H
H
*
L
L
*
H
*
*
H
L
H
*
*
D
OUT
D
IN
High-Z
High-Z
High-Z
I
DDO
I
DDO
I
DDO
I
DDS
I
DDS
MAXIMUM RATINGS
SYMBOL
V
DD
V
IN
V
I/O
P
D
T
solder
T
stg
ITEM
Power Supply Voltage
Input Voltage
Input and Output Voltage
Power Dissipation
Soldering
Temperature
RATING
-0.3~7.0
*-0.3~7.0
-0-5-VDD+0.5
1.0/0.6**
260-10
-55~150
0-70
UNIT
v
v
v
W
°C sec
°C
°C
Storage Temperature
T
opr
Operating Temperature
* -3.0V
at pulse width 50ns MAX. **Flat package
D.C RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
V
DD
Power Supply Voltage
V
IH
Input High Voltage
V
IL
V
DH
Input Low Voltage
Data-Retention Supply Voltage
MIN.
4.5
2.2
-0.3
2.0
Typ.
5.0
-
-
-
MAX.
5.5
V
DD
+0.3
0.8
5.5
UNIT
v
v
V
V
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
D.C and OPERATING CHARACTERISTICS (Ta=0~70
°C
,
V
DD
= 5V±10%)
SYMBOL
I
IL
I
OH
I
OL
I
LO
PARAMETER
Input Leakage
Current
Output High Current
Output Low Current
Output Leakage Current
TEST CONDITION
V
IN=
O~V
DD
VOH-2-4V
VOL-0.4V
V
IH
or CE2-VOL or
\CE1 = V
IH
or CE2=V
OL
0r R/W = V
IL
or \OE=V
IH
V
OUT
=0~V
DD
t
cycle
=1.0us
TC5565APL-10 t
cycle
TC556SAFL-10 =100ns
V
DD
=5.5V
\CE1=V
IL
CE2=V
IH
Other input=
V
IH
/V
IL
MIN. TYP. MAX. UNIT
-
-1.0
4.0
-
-
-
-
-
±1.0
10
-
-
45
±1.0
uA
mA
mA
uA
mA
mA
I
DDO1
TC5565APL-12 t
cycle
TC5565AFL-12 =120ns
-
-
40
mA
Operating Current
TC5565A?L-15 t
cycle
TC5565AFL-15 =150ns
t
cycle=1.0us
TC5565APL-10
t
cycle
=100ns
V
DD=
5.5V
\CEl=O.2V
CE2=V
DD
–0.2V
Other lnput=
V
DD
- 0.2V/0.2V
TC5565AFL-10
TC5565AFL-12
t
cycle
=120ns
TC5565AFL-12
TC5565APL-15
TC5565AFL-15
t
cycle
=150ns
-
-
35
mA
-
-
5
mA
-
-
40
mA
I
DD02
-
-
35
mA
-
-
30
3
100
50
mA
mA
uA
uA
I
DDS1
*I
DDS2
Note *
Standby Current
\Cel = V
IH
or CE2 = V
IL
\CE1 = V
DD
– 0.2V or
CE2 = 0.2V
V
DD
= 5.5V
V
DD
= 3.0V
-
-
2
1
In standby mode with \CE1>= V
DD
– 0.2V, these specification limits are guaranteed under the condition of
CE2 >= V
DD
– 0.2V or CE2 <= 0.2V.
CAPACITANCE
(Ta=25
°C
)
SYMBOL
PARAMETER
Input Capacitance
C
IN
Output Capacitance
C
OUT
* This parameter periodically sampled is not 100% tested.
TEST
CONDITION
V
IN
= GND
V
OUT
= GND
MIN.
-
-
TYP.
-
-
MAX.
10
10
UNIT
pF
pF
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
A.C. CHARACTERISTICS
(Ta=0~70
°C
, V
DD
= 5V±10%)
Read Cycle
SYMBOL PARAMETER
TC5565APL-10
TC5565AFL-10
MIN. MAX.
100
-
-
100
-
100
-
100
-
50
10
5
-
-
20
-
-
35
35
-
TC5565APL-12 TC5565APL-15
TC5565AFL-12 TC5565AFL-15
MIN.
MAX. MIN.
MAX
120
-
150
-
-
120
-
150
-
120
-
150
-
120
-
150
-
60
-
70
10
5
-
-
20
-
-
40
40
-
15
5
-
-
20
-
-
50
50
-
t
RC
t
ACC
t
COL
t
C02
t
OE
t
COE
t
OEE
t
OD
t
ODO
t
OH
Read Cycle Time
Address Access Time
\CE1 Access Time
CE2 Access Time
Output Enable to Output Valid
Chip Enable (\CE1, CE2) to
Output in Low-Z
Output Enable to Output in Low-Z
Chip Enable (CE1, CE2) to
Output in High-Z
Output Enable to Output in High-Z
Output Data Hold Time
Write Cycle
SYMBOL
PARAMETER
TC5565APL-10
TC5565AFL-10
MIN. MAX.
100
-
60
-
80
-
0
-
0
-
-
35
5
-
40
-
0
-
TC5565APL-12 TC5565APL- 5
TC5565AFL-12 TC5565AFL- 5
MIN.
MAX. MIN. MAX..
120
-
150
-
70
-
90
-
85
-
100
-
0
-
0
-
0
-
0
-
0
40
-
50
5
-
10
-
50
-
60
-
0
-
0
-
Write Cycle Time
Write Pulse Width
Chip Selection to End of Write
t
AS
Address Set up Time
r
WR
Write Recovery Time
t
ODW
R/W to Output High-Z
r
OEW
R/W to Output Low-Z
t
DS
Data Set up Time
t
DH
Data Hold Time
A.C. TEST CONDITION
Output Load
Input Pulse Level
Timing Measurement
Reference Level
t
r,
t
f
t
WC
t
WP
t
CW
V
IN
V
OUT
: 100pF + 1 TTL Gate
: 0.6V, 2.4V
: 0.8V, 2.2V
: 0.8V, 2.2V
: 5ns
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