IS25LP128
128M-BIT
3V- MULTI I/O SERIAL FLASH MEMORY WITH 133MHZ SPI
BUS & QUAD I/O (QPI) DTR INTERFACE
DATA SHEET
IS25LP128
128M-BIT
3V- MULTI I/O SERIAL FLASH MEMORY WITH 133MHZ SPI BUS
& QUAD I/O (QPI) DTR INTERFACE
FEATURES
Industry Standard Serial Interface
-
IS25LP128:128M-bit/16M-byte
-
256-bytes per Programmable Page
-
Supports standard SPI, Fast, Dual, Dual
I/O, QPI, DTR, Dual DTR I/O, and QPI
DTR SPI
-
Supports Serial Flash Discoverable
Parameters (SFDP)
High Performance Serial Flash (SPI)
-
50MHz Normal and 133Mhz Fast Read
-
532 MHz equivalent QPI SPI
-
DTR (Dual Transfer Rate) up to 66MHz
-
Selectable dummy cycles
-
Configurable drive strength
-
Supports SPI Modes 0 and 3
-
More than 100,000 erase/program cycles
-
More than 20-year data retention
Flexible & Efficient Memory Architecture
-
Chip Erase:128Mbit with Uniform:
Sector/Block Erase (4K/32K/64K-Byte)
-
Program 1 to 256 bytes per page
-
Program/Erase Suspend & Resume
Efficient Read and Program modes
-
Low Instruction Overhead Operations
-
Continuous Read 8/16/32/64-Byte Wrap
-
Selectable burst length
-
QPI for reduced instruction overhead
-
Allows XIP operations (execute in place)
Low Power with Wide Temp.
Ranges
-
Single 2.3V to 3.6V Voltage Supply
-
10 mA Active Read Current
-
5 µA Standby Current
-
Deep Power Down
-
Temp Grades:
Extended: -40°C to +105°C
Auto Grade: up to +125°C (call factory)
-
-
-
-
Advanced Security Protection
Software and Hardware Write Protection
Power Supply lock protect
4x256-Byte dedicated security area
with user-lockable bits, (OTP) One
Time Programmable Memory
128 bit Unique ID for each device
Industry Standard Pin-out & Packages
-
JM =16-pin SOIC 300mil
-
JB = 8-pin SOIC 208mil
-
JF = 8-pin VSOP 208mil
-
JK = 8-pin WSON 6x5mm
-
JL = 8-pin WSON 8x6mm
-
KGD (call factory)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0A
4/03/2014
2
IS25LP128
GENERAL DESCRIPTION
The IS25LP128 Serial Flash memory offers a storage solution with the flexibility and performance in a simplified
pin count package. ISSI’s “Industry Standard Serial Interface” flash are for systems that have limited space,
pins, and power. The IS25LP128 are accessed through a 4-wire SPI Interface consisting of a Serial Data Input
(Sl), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which also serve as multi-
function I/O (see pin descriptions).
The device supports the standard Serial Peripheral Interface (SPI), Dual/Quad output (SPI), and Dual/Quad I/O
(SPI). Clock frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4)
allowing more than 66MBytes/S of throughput. The IS25xP series of flash adds support for DTR (Double
Transfer Rate) commands that transfer address and read data on both edges of the clock. These transfer rates
can outperform 16-bit Parallel Flash memories allowing for efficient memory access for a XIP (execute in place)
operation.
The memory array is organized into programmable pages of 256-bytes each. The IS25LP128 supports page
program mode where 1 to 256 bytes of data can be programmed into the memory with one command. QPI
(Quad Peripheral Interface) supports 2-cycles instruction cycles further reducing instruction times. Pages can
be erased in groups of 4K-byte sectors, 32K-byte blocks, 64K-byte blocks, and/or the entire chip. The uniform
sectors and blocks allow greater flexibility for a variety of applications requiring solid data retention.
GLOSSARY
Standard SPI
The IS25LP032/064 is accessed through a 4-wire SPI Interface consisting of Serial Data Input (Sl), Serial Data
Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are inputted through the SI pin to
encode instructions, addresses, or input data to the device on the rising edge of SCK. The DO pin is used to
read data or check the status of the device on the falling edge of SCK. This device supports SPI bus operation
mode (0,0) and (1,1).
Mutil I/O SPI
The IS25LP032/064 allows accessing enhanced SPI protocol to use Dual output, Dual input and output, and
Quad input and output operation. Executing these instructions through SPI mode will achieve double or
quadruple the transfer bandwidth for READ and PROGRAM.
Quad I/O (QPI)
The IS25LP032/064 can enable QPI protocol by issuing an “Enter QPI mode (35h)” command. The QPI mode
uses four IO pins for input and output to reduce SPI instruction overhead and increase output bandwidth. QPI
mode can exit by issuing an “Exit QPI (F5h) command. A power reset or software reset can also return the
device into the standard SPI mode. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD#
pins become IO2 and IO3 respectively during QPI mode.
DTR
In addition to SPI and QPI features, IS25LP032/064 also supports DTR READ. DTR allows high data throughput
while running at lower clock frequencies. As DTR READ option uses both rising and falling clock to drive output,
the dummy cycles are reduced by half as well.
Programmable drive strength and Selectable burst setting.
The IS25LP032/064 offers programmable output drive strength and selectable burst (wrap) length features to
increase the efficiency and performance of READ operations. The driver strength and burst setting features are
controlled by setting READ registers. A total of six different drive strengths and four different burst sizes
(8/16/32/64Bytes) are selectable.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0A
4/03/2014
3
IS25LP128
TABLE OF CONTENTS
1.
2.
3.
4.
5.
6.
PIN CONFIGURATION ................................................................................................................................................. 6
PIN DESCRIPTIONS .................................................................................................................................................... 7
BLOCK DIAGRAM ........................................................................................................................................................ 8
SPI MODES DESCRIPTION ......................................................................................................................................... 9
SYSTEM CONFIGURATION ...................................................................................................................................... 11
5.1 BLOCK/SECTOR ADDRESSES ........................................................................................................................... 11
REGISTERS ............................................................................................................................................................... 12
6.1. STATUS REGISTER ............................................................................................................................................ 12
6.2. FUNCTION REGISTER ....................................................................................................................................... 14
6.3 READ REGISTERS .............................................................................................................................................. 15
7.
PROTECTION MODE ................................................................................................................................................. 17
7.1 HARDWARE WRITE PROTECTION .................................................................................................................... 17
7.2 SOFTWARE WRITE PROTECTION ..................................................................................................................... 17
8.
DEVICE OPERATION................................................................................................................................................. 18
8.1 NORMAL READ OPERATION (NORD, 03h) ........................................................................................................ 20
8.2 FAST READ DATA OPERATION (FRD, 0Bh) ...................................................................................................... 21
8.3 HOLD OPERATION .............................................................................................................................................. 23
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ............................................................................................ 23
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh) .................................................................................... 25
8.6 FAST READ QUAD I/O OPERATION (FRQIO, EBh) ........................................................................................... 26
8.7 PAGE PROGRAM OPERATION (PP, 02h) .......................................................................................................... 29
8.8 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h) .......................................................................... 31
8.9 ERASE OPERATION ............................................................................................................................................ 32
8.10 SECTOR ERASE OPERATION (SER, D7h/20h) ................................................................................................ 33
8.11 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................................. 34
8.12 CHIP ERASE OPERATION (CER, C7h/60h) ...................................................................................................... 36
8.13 WRITE ENABLE OPERATION (WREN, 06h) ..................................................................................................... 37
8.14 WRITE DISABLE OPERATION (WRDI, 04h) ..................................................................................................... 38
8.15 READ STATUS REGISTER OPERATION (RDSR, 05h) .................................................................................... 39
8.16 WRITE STATUS REGISTER OPERATION (WRSR, 01h) .................................................................................. 40
8.17 READ FUNCTION REGISTER OPERATION (RDFR, 48h) ................................................................................ 41
8.18 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h) .............................................................................. 42
8.19 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QIOEN,35h; QIODI,F5h) ................... 43
8.20 PROGRAM/ERASE SUSPEND & RESUME ...................................................................................................... 44
8.21 DEEP POWER DOWN (DP, B9h) ....................................................................................................................... 45
8.22 RELEASE DEEP POWER DOWN (RDPD, ABh) ................................................................................................ 46
8.23 SET READ PARAMETERS OPERATION (SRP, C0h) ....................................................................................... 46
8.24 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................................. 49
8.25 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh) ............................................ 51
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0A
4/03/2014
4
IS25LP128
8.26 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) .......................................... 52
8.27 READ UNIQUE ID NUMBER (RDUID, 4Bh) ....................................................................................................... 54
8.28 READ SFDP OPERATION (RDSFDP, 5Ah) ....................................................................................................... 55
8.29 NO OPERATION (NOP, 00h).............................................................................................................................. 62
8.30 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h) .............................................. 62
8.31 MODE RESET OPERATION (RSTM, FFh) ........................................................................................................ 63
8.32 SECURITY INFORMATION ROW ...................................................................................................................... 64
8.33 INFORMATION ROW ERASE OPERATION (IRER, 64h) .................................................................................. 64
8.34 INFORMATION ROW PROGRAM OPERATION (IRP, 62h)............................................................................... 65
8.35 INFORMATION ROW READ OPERATION (IRRD, 68h) .................................................................................... 66
8.36 FAST READ DTR MODE OPERATION (FRDTR, 0Dh) ...................................................................................... 67
8.37 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh).................................................................... 68
8.38 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh) ................................................................... 69
8.39 SECTOR LOCK/UNLOCK FUNCTIONS ............................................................................................................. 70
9.
ELECTRICAL CHARACTERISTICS ........................................................................................................................... 72
9.1 ABSOLUTE MAXIMUM RATINGS
(1)
.................................................................................................................... 72
9.2 OPERATING RANGE ........................................................................................................................................... 72
9.3 DC CHARACTERISTICS ...................................................................................................................................... 72
9.4 AC MEASUREMENT CONDITIONS ..................................................................................................................... 73
9.5 AC CHARACTERISTICS ...................................................................................................................................... 74
9.6 SERIAL INPUT/OUTPUT TIMING
(1)
.................................................................................................................... 75
9.7 POWER-UP AND POWER-DOWN ....................................................................................................................... 75
9.8 PROGRAM/ERASE PERFORMANCE .................................................................................................................. 76
10.
PACKAGE TYPE INFORMATION ......................................................................................................................... 78
10.1 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (JB)
10.2 8-Contact Ultra-Thin Small Outline No-Lead WSON (6x5mm) (JK)
10.3 8-Contact Ultra-Thin Small Outline No-Lead WSON (8x6mm) (JL)
10.4 8-Pin 208mil VSOP Package (JF)
(1)
(1)
(1)
(1)
........................................ 77
................................................................. 78
................................................................. 79
................................................................................................................... 80
(1)
10.4 16-lead Plastic Small Outline package (300 mils body width) (JM)
................................................................. 8
1
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0A
4/03/2014
5