Rev: 032609
DS34S101, DS34S102, DS34S104, DS34S108
Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
compliant devices allow up to eight E1, T1 or serial
streams or one high-speed E3, T3, STS-1 or serial
stream to be transported transparently over IP, MPLS
or Ethernet networks. Jitter and wander of recovered
clocks conform to G.823/G.824, G.8261, and TDM
specifications. TDM data is transported in up to 64
individually configurable bundles. All standards-
based TDM-over-packet mapping methods are
supported except AAL2. Frame-based serial HDLC
data flows are also supported. The high level of
integration available with the DS34S10x devices
minimizes cost, board space, and time to market.
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Features
Transport of E1, T1, E3, T3 or STS-1 TDM or
Other CBR Signals Over Packet Networks
Full Support for These Mapping Methods:
SAToP, CESoPSN, TDMoIP (AAL1), HDLC,
Unstructured, Structured, Structured with CAS
Adaptive Clock Recovery, Common Clock,
External Clock and Loopback Timing Modes
On-Chip TDM Clock Recovery Machines, One
Per Port, Independently Configurable
Clock Recovery Algorithm Handles Network
PDV, Packet Loss, Constant Delay Changes,
Frequency Changes and Other Impairments
64 Independent Bundles/Connections
Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
VLAN Support According to 802.1p and 802.1Q
10/100 Ethernet MAC Supports MII/RMII/SSMII
Selectable 32-Bit, 16-Bit or SPI Processor Bus
Operates from Only Two Clock Signals, One for
Clock Recovery and One for Packet Processing
Glueless SDRAM Buffer Management
Low-Power 1.8V Core, 3.3V I/O
Applications
TDM Circuit Extension Over PSN
o
Leased-Line Services Over PSN
o
TDM Over GPON/EPON
o
TDM Over Cable
o
TDM Over Wireless
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC-Based Traffic Transport Over PSN
See detailed feature list in Section
7.
Functional Diagram
CPU
Bus
Ordering Information
PART
DS34S101GN
DS34S101GN+
DS34S102GN
DS34S102GN+
DS34S104GN
DS34S104GN+
DS34S108GN
DS34S108GN+
PORTS TEMP RANGE PIN-PACKAGE
1
1
2
2
4
4
8
8
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
256 TECSBGA
256 TECSBGA
256 TECSBGA
256 TECSBGA
256 TECSBGA
256 TECSBGA
484 HSBGA
484 HSBGA
DS34S108
TDM
Interfaces
Circuit
Emulation
Engine
10/100
Ethernet
MAC
Clock
xMII
Interface
Manager
Buffer
Adapters
SDRAM
Interface
Clock Inputs
+Denotes
a lead(Pb)-free/RoHS-compliant package (explanation).
_________________________________________________________
Maxim Integrated Products
1
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, go to:
www.maxim-ic.com/errata.
For pricing, delivery, and ordering
information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Table of Contents
1. INTRODUCTION ................................................................................................................................. 7
2. ACRONYMS AND GLOSSARY .......................................................................................................... 8
3. APPLICABLE STANDARDS ............................................................................................................ 10
4. DETAILED DESCRIPTION ............................................................................................................... 11
5. APPLICATION EXAMPLES .............................................................................................................. 12
6. BLOCK DIAGRAM ............................................................................................................................ 14
7. FEATURES ....................................................................................................................................... 15
8. OVERVIEW OF MAJOR OPERATIONAL MODES ........................................................................... 17
9. PIN DESCRIPTIONS ......................................................................................................................... 18
9.1 S
HORT
P
IN
D
ESCRIPTIONS
.............................................................................................................. 18
9.2 D
ETAILED
P
IN
D
ESCRIPTIONS
......................................................................................................... 20
10. FUNCTIONAL DESCRIPTION ........................................................................................................ 28
10.1 P
OWER
-S
UPPLY
C
ONSIDERATIONS
............................................................................................... 28
10.2 CPU I
NTERFACE
.......................................................................................................................... 28
10.3 SPI I
NTERFACE
............................................................................................................................ 31
10.3.1 SPI Operation .................................................................................................................................... 31
10.3.2 SPI Modes ......................................................................................................................................... 32
10.3.3 SPI Signals ........................................................................................................................................ 33
10.3.4 SPI Protocol ....................................................................................................................................... 33
10.4 C
LOCK
S
TRUCTURE
...................................................................................................................... 36
10.5 R
ESET AND
P
OWER
-D
OWN
........................................................................................................... 37
10.6 TDM-
OVER
-P
ACKET
B
LOCK
.......................................................................................................... 37
10.6.1 Packet Formats .................................................................................................................................. 37
10.6.2 Typical Application ............................................................................................................................. 47
10.6.3 Clock Recovery .................................................................................................................................. 48
10.6.4 Timeslot Assigner (TSA)..................................................................................................................... 49
10.6.5 CAS Handler ...................................................................................................................................... 50
10.6.6 AAL1 Payload Type Machine ............................................................................................................. 54
10.6.7 HDLC Payload Type Machine............................................................................................................. 57
10.6.8 RAW Payload Type Machine .............................................................................................................. 58
10.6.9 SDRAM and SDRAM Controller ......................................................................................................... 62
10.6.10 Jitter Buffer Control (JBC)................................................................................................................. 63
10.6.11 Queue Manager ............................................................................................................................... 66
10.6.12 Ethernet MAC................................................................................................................................... 78
10.6.13 Packet Classifier .............................................................................................................................. 81
10.6.14 Packet Trailer Support ...................................................................................................................... 84
10.6.15 Counters and Status Registers ......................................................................................................... 85
10.6.16 Connection Level Redundancy ......................................................................................................... 85
10.6.17 OAM Signaling ................................................................................................................................. 86
10.7 G
LOBAL
R
ESOURCES
................................................................................................................... 87
10.8 P
ER
-P
ORT
R
ESOURCES
................................................................................................................ 87
10.9 D
EVICE
I
NTERRUPTS
.................................................................................................................... 87
11. DEVICE REGISTERS...................................................................................................................... 89
11.1 A
DDRESSING
................................................................................................................................ 89
11.2 T
OP
-L
EVEL
M
EMORY
M
AP
............................................................................................................ 90
Rev: 032609
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
11.3 G
LOBAL
R
EGISTERS
..................................................................................................................... 91
11.4 TDM-
OVER
-P
ACKET
R
EGISTERS
................................................................................................... 93
11.4.1 Configuration and Status Registers .................................................................................................... 94
11.4.2 Bundle Configuration Tables ............................................................................................................ 108
11.4.3 Counters .......................................................................................................................................... 117
11.4.4 Status Tables ................................................................................................................................... 120
11.4.5 Timeslot Assignment Tables............................................................................................................. 122
11.4.6 CPU Queues .................................................................................................................................... 124
11.4.7 Transmit Buffers Pool ....................................................................................................................... 129
11.4.8 Jitter Buffer Control .......................................................................................................................... 130
11.4.9 Transmit Software CAS .................................................................................................................... 134
11.4.10 Receive Line CAS .......................................................................................................................... 136
11.4.11 Clock Recovery .............................................................................................................................. 137
11.4.12 Receive SW Conditioning Octet Select ........................................................................................... 138
11.4.13 Receive SW CAS ........................................................................................................................... 139
11.4.14 Interrupt Controller ......................................................................................................................... 140
11.4.15 Packet Classifier ............................................................................................................................ 147
11.4.16 Ethernet MAC................................................................................................................................. 148
12. JTAG INFORMATION ....................................................................................................................158
13. DC ELECTRICAL CHARACTERISTICS ........................................................................................163
14. AC TIMING CHARACTERISTICS ..................................................................................................164
14.1 CPU I
NTERFACE
T
IMING
..............................................................................................................164
14.2 SPI I
NTERFACE
T
IMING
................................................................................................................165
14.3 SDRAM I
NTERFACE
T
IMING
.........................................................................................................166
14.4 TDM-
OVER
-P
ACKET
TDM I
NTERFACE
T
IMING
...............................................................................169
14.5 E
THERNET
MII/RMII/SSMII I
NTERFACE
T
IMING
.............................................................................172
14.6 CLAD
AND
S
YSTEM
C
LOCK
T
IMING
..............................................................................................174
14.7 JTAG I
NTERFACE
T
IMING
............................................................................................................175
15. APPLICATIONS .............................................................................................................................176
15.1 C
ONNECTING A
S
ERIAL
I
NTERFACE
T
RANSCEIVER
.........................................................................176
15.2 C
ONNECTING AN
E
THERNET
PHY
OR
MAC ...................................................................................177
15.3 I
MPLEMENTING
C
LOCK
R
ECOVERY IN
H
IGH
S
PEED
A
PPLICATIONS
..................................................179
15.4 C
ONNECTING A
M
OTOROLA
MPC860 P
ROCESSOR
.......................................................................179
15.5 W
ORKING IN
SPI M
ODE
...............................................................................................................183
15.6 C
ONNECTING
SDRAM D
EVICES
...................................................................................................183
16. PIN ASSIGNMENTS ......................................................................................................................184
16.1 B
OARD
D
ESIGN FOR
M
ULTIPLE
DS34S101/2/4 D
EVICES
...............................................................184
16.2 DS34S101 P
IN
A
SSIGNMENT
.......................................................................................................190
16.3 DS34S102 P
IN
A
SSIGNMENT
.......................................................................................................191
16.4 DS34S104 P
IN
A
SSIGNMENT
.......................................................................................................192
16.5 DS34S108 P
IN
A
SSIGNMENT
.......................................................................................................193
17. PACKAGE INFORMATION............................................................................................................197
18. THERMAL INFORMATION ............................................................................................................197
19. DATA SHEET REVISION HISTORY ..............................................................................................198
15.4.1 Connecting the Bus Signals.............................................................................................................. 179
15.4.2 Connecting the H_READY_N Signal ................................................................................................ 182
Rev: 032609
3 of 198
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
List of Figures
Figure 5-1. TDMoP in a Metropolitan Packet Switched Network ........................................................................... 12
Figure 5-2. TDMoP in Cellular Backhaul............................................................................................................... 13
Figure 6-1. Top-Level Block Diagram ................................................................................................................... 14
Figure 10-1. CPU Interface Functional Diagram .................................................................................................. 28
Figure 10-2. Write Access, 32-Bit Bus ................................................................................................................. 29
Figure 10-3. Read Access, 32-Bit Bus................................................................................................................. 30
Figure 10-4. Read/Write Access, 16-Bit Bus........................................................................................................ 30
Figure 10-5. Write Access to the SDRAM, 16-Bit Bus .......................................................................................... 31
Figure 10-6. Read Access to the SDRAM, 16-Bit Bus.......................................................................................... 31
Figure 10-7. SPI Interface with One Slave ........................................................................................................... 32
Figure 10-8. SPI Interface Timing, SPI_CP=0 ..................................................................................................... 32
Figure 10-9. SPI Interface Timing, SPI_CP=1 ..................................................................................................... 32
Figure 10-10. TDM-over-Packet Encapsulation Formats...................................................................................... 38
Figure 10-11. Single VLAN Tag Format............................................................................................................... 39
Figure 10-12. Stacked VLAN Tag Format............................................................................................................ 39
Figure 10-13. UDP/IPv4 Header Format.............................................................................................................. 39
Figure 10-14. UDP/IPv6 Header Format.............................................................................................................. 40
Figure 10-15. MPLS Header Format ................................................................................................................... 41
Figure 10-16. MEF Header Format...................................................................................................................... 41
Figure 10-17. L2TPv3/IPv4 Header Format ......................................................................................................... 42
Figure 10-18. L2TPv3/IPv6 Header Format ......................................................................................................... 43
Figure 10-19. Control Word Format ..................................................................................................................... 43
Figure 10-20. RTP Header Format ...................................................................................................................... 44
Figure 10-21. VCCV OAM Packet Format ........................................................................................................... 45
Figure 10-22. UDP/IP-Specific OAM Packet Format ............................................................................................ 46
Figure 10-23. TDM Connectivity over a PSN ....................................................................................................... 47
Figure 10-24. TDMoP Packet Format in a Typical Application ............................................................................. 47
Figure 10-25. TDMoMPLS Packet Format in a Typical Application ...................................................................... 48
Figure 10-26. CAS Transmitted in the TDM-to-Ethernet Direction ........................................................................ 50
Figure 10-27. Transmit SW CAS Table Format for E1 and T1-ESF Interfaces ..................................................... 51
Figure 10-28. Transmit SW CAS Table Format for T1-SF Interfaces.................................................................... 51
Figure 10-29. E1 MF Interface RSIG Timing Diagram (two_clocks=1) ................................................................. 51
Figure 10-30. T1 ESF Interface RSIG Timing Diagram (two_clocks=0) ................................................................ 52
Figure 10-31. T1 SF Interface RSIG (two_clocks=0) – Timing Diagram ............................................................... 52
Figure 10-32. CAS Transmitted in the Ethernet-to-TDM Direction ........................................................................ 53
Figure 10-33. E1 MF Interface TSIG Timing Diagram .......................................................................................... 54
Figure 10-34. T1 ESF Interface TSIG Timing Diagram ........................................................................................ 54
Figure 10-35. T1 SF Interface TSIG Timing Diagram ........................................................................................... 54
Figure 10-36. AAL1 Mapping, General ................................................................................................................ 55
Figure 10-37. AAL1 Mapping, Structured-Without-CAS Bundles .......................................................................... 56
Figure 10-38. HDLC Mapping ............................................................................................................................. 57
Figure 10-39. SAToP Unstructured Packet Mapping............................................................................................ 58
Figure 10-40. CESoPSN Structured-Without-CAS Mapping................................................................................. 59
Figure 10-41. CESoPSN Structured-With-CAS Mapping (No Frag, E1 Example) ................................................. 59
Figure 10-42. CESoPSN Structured-With-CAS Mapping (No Frag, T1-ESF Example) ......................................... 60
Figure 10-43. CESoPSN Structured-With-CAS Mapping (No Frag, T1-SF Example) ........................................... 60
Figure 10-44. CESoPSN Structured-With-CAS Mapping (Frag, E1 Example) ...................................................... 61
Figure 10-45. SDRAM Access through the SDRAM Controller............................................................................. 63
Figure 10-46. Loop Timing in TDM Networks....................................................................................................... 63
Figure 10-47. Timing in TDM-over-Packet ........................................................................................................... 64
Figure 10-48. Jitter Buffer Parameters................................................................................................................. 65
Figure 10-49. TDM-over-Packet Data Flow Diagram ........................................................................................... 67
Figure 10-50. Free Buffer Pool Operation ............................................................................................................ 71
Figure 10-51. TDM-to-Ethernet Flow ................................................................................................................... 72
Figure 10-52. Ethernet-to-TDM Flow ................................................................................................................... 73
Rev: 032609
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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Figure 10-53. TDM-to-TDM Flow......................................................................................................................... 74
Figure 10-54. TDM-to-CPU Flow ......................................................................................................................... 75
Figure 10-55. CPU-to-TDM Flow ......................................................................................................................... 76
Figure 10-56. CPU-to-Ethernet Flow ................................................................................................................... 77
Figure 10-57. Ethernet-to-CPU Flow ................................................................................................................... 78
Figure 10-59. Ethernet MAC ............................................................................................................................... 79
Figure 10-60. Format of TDMoIP Packet with VLAN Tag ..................................................................................... 82
Figure 10-61. Format of TDMoMPLS Packet with VLAN Tag ............................................................................... 82
Figure 10-62. Format of TDMoMEF Packet with VLAN Tag ................................................................................. 82
Figure 10-63. Structure of Packets with Trailer .................................................................................................... 85
Figure 11-1. 16-Bit Addressing ............................................................................................................................ 89
Figure 11-2. 32-Bit Addressing ............................................................................................................................ 89
Figure 11-3. Partial Data Elements (shorter than 16 bits)..................................................................................... 89
Figure 11-4. Partial Data Elements (16 to 32 bits long) ........................................................................................ 90
Figure 12-1. JTAG Block Diagram ..................................................................................................................... 158
Figure 12-2. JTAG TAP Controller State Machine ............................................................................................. 159
Figure 14-1. RST_SYS_N Timing...................................................................................................................... 164
Figure 14-2. CPU Interface Write Cycle Timing ................................................................................................. 165
Figure 14-3. CPU Interface Read Cycle Timing ................................................................................................. 165
Figure 14-4. SPI interface Timing (SPI_CP = 0) ................................................................................................ 166
Figure 14-5. SPI interface Timing (SPI_CP = 1) ................................................................................................ 166
Figure 14-6. SDRAM Interface Write Cycle Timing ............................................................................................ 167
Figure 14-7. SDRAM Interface Read Cycle Timing ............................................................................................ 168
Figure 14-8. TDMoP TDM Timing, One-Clock Mode (Two_clocks=0, Tx_sample=1) ......................................... 169
Figure 14-9. TDMoP TDM Timing, One Clock Mode (Two_clocks=0, Tx_sample=0) ......................................... 170
Figure 14-10. TDMoP TDM Timing, Two Clock Mode (Two_clocks=1, Tx_sample=1, Rx_sample=1) ................ 170
Figure 14-11. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=0)............... 170
Figure 14-12. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=1)............... 171
Figure 14-13. TDMoP TDM Timing,Two Clocks Mode (Two_clocks=1, Tx_sample=1, Rx_sample=0)................ 171
Figure 14-14. MII Management Interface Timing ............................................................................................... 172
Figure 14-15. MII Interface Output Signal Timing............................................................................................... 172
Figure 14-16. MII Interface Input Signal Timing ................................................................................................. 173
Figure 14-17. RMII Interface Output Signal Timing ............................................................................................ 173
Figure 14-18. RMII Interface Input Signal Timing ............................................................................................... 173
Figure 14-19. SSMII Interface Output Signal Timing .......................................................................................... 174
Figure 14-20. SSMII Interface Input Signal Timing............................................................................................. 174
Figure 14-21. JTAG Interface Timing Diagram .................................................................................................. 175
Figure 15-1. Connecting Port 1 to a Serial Transceiver...................................................................................... 176
Figure 15-2. Connecting the Ethernet Port to a PHY in MII Mode ...................................................................... 177
Figure 15-3. Connecting the Ethernet Port to a MAC in MII Mode ...................................................................... 177
Figure 15-4. Connecting the Ethernet Port to a PHY in RMII Mode .................................................................... 177
Figure 15-5. Connecting the Ethernet Port to a MAC in RMII Mode ................................................................... 178
Figure 15-6. Connecting the Ethernet Port to a PHY in SSMII Mode.................................................................. 178
Figure 15-7. Connecting the Ethernet Port to a MAC in SSMII Mode ................................................................. 178
Figure 15-8. External Clock Multiplier for High Speed Applications .................................................................... 179
Figure 15-9. 32-Bit CPU Bus Connections......................................................................................................... 180
Figure 15-10. 16-Bit CPU Bus Connections....................................................................................................... 181
Figure 15-11. Connecting the H_READY_N Signal to the MPC860 TA Pin ....................................................... 182
Figure 15-12. Internal CPLD Logic to Synchronize H_READY_N to the MPC860 Clock..................................... 182
Figure 16-1. DS34S101 Pin Assignment (TE-CSBGA Package) ........................................................................ 190
Figure 16-2. DS34S102 Pin Assignment (TE-CSBGA Package) ........................................................................ 191
Figure 16-3. DS34S104 Pin Assignment (TE-CSBGA Package) ........................................................................ 192
Figure 16-4. DS34S108 Pin Assignment (HSBGA Package) ............................................................................. 196
Rev: 032609
5 of 198
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