Data Sheet
February 1998
T7503 Dual PCM Codec with Filters
Features
s
s
s
s
Applications
s
s
s
+5 V only
Automatic powerdown mode
Low-power, latch-up-free CMOS technology
On-chip sample and hold, autozero, and precision
voltage reference
Differential architecture for high noise immunity
and power supply rejection
Automatic master clock frequency selection
2.048 MHz or 4.096 MHz fixed data rate
Frame sync controlled channel swapping
Differential analog I/O
300
Ω
output drivers
Operating temperature range: –40
°
C to +85
°
C
µ
-law companding
Speakerphone
Telephone answering device (TAD)
POTS for ISDN
Description
The T7503 device is a single-chip, two-channel
µ
-law PCM codec with filters. This integrated circuit
provides analog-to-digital and digital-to-analog
conversion. It provides the transmit and receive
filtering necessary to interface a voice telephone
circuit to a time-division multiplexed (TDM) system.
The device features a differential transmit amplifier,
and the power receive amplifier is capable of driving
600
Ω
differentially. PCM timing is defined by a single
frame sync pulse. This device operates in a delayed
timing mode (digital data is valid one clock cycle after
frame sync goes high). The T7503 is packaged in a
20-pin SOJ.
s
s
s
s
s
s
s
s
GS
X
0
D
X
VF
X
IN0
VF
X
IP0
VCM0
–
+
+2.4 V
FILTER
NETWORK
ENCODER
PCM
INTERFACE
D
R
GNDD
CHANNEL 0
FS
VF
R
OP0
VF
R
ON0
FILTER
NETWORK
DECODER
POWERDOWN
CONTROL
INTERNAL TIMING
& CONTROL
GS
X
1
VF
X
IN1
VF
X
IP1
VCM1
VF
R
OP1
VF
R
ON1
5-3609.b
MCLK
CHANNEL 1
BIAS
CIRCUITRY
&
REFERENCE
V
DD
(1)
GNDA (2)
Figure 1. Block Diagram
T7503 Dual PCM Codec with Filters
Data Sheet
February 1998
Functional Description
The T7503 has one frame sync (FS) input that determines transmit and receive data timing for both channels. The
width of the FS pulse determines the order of the two channels on the PCM buses. If FS is nominally one MCLK
period wide (see Figure 5), the data for channel 0 is first. If FS is nominally two or more MCLK periods wide (Figure
6), the data for channel 1 is first. During a single 125
µ
s frame, the frame sync input is supplied a single pulse.
The frequency of the master clock must be either 2.048 MHz or 4.096 MHz. Internal circuitry determines the
master clock frequency during the powerup reset interval.
Powerdown is achieved by removing the FS pulse for at least 500
µ
s with MCLK active, after which MCLK may be
removed. Both channels are powered down together. Powerdown is not guaranteed if MCLK is lost, unless the
device is already in the powerdown mode.
R
FN
R
IN
R
IP
GS
Xn
VF
X
INn
–
VF
X
IPn
VCM0
2.4 V
+
TO
CODEC
FILTERS
R
FP
GAIN =
R
FN
R
IN
5-3787
Figure 2. Typical Analog Input Section
Pin Information
VF
R
OP0
VF
R
ON0
GNDA0
VF
X
IN0
VF
X
IP0
GS
X
0
VCM0
V
DD
MCLK
GNDD
1
2
3
4
5
6
7
8
9
10
T - 7503 - - - EL
20
19
18
17
16
15
14
13
12
11
VF
R
OP1
VF
R
ON1
GNDA1
VF
X
IN1
VF
X
IP1
GS
X
1
VCM1
FS
D
R
D
X
5-3788
Figure 3. Pin Diagram
2
Lucent Technologies Inc.
Data Sheet
February 1998
T7503 Dual PCM Codec with Filters
Pin Information
(continued)
Table 1. Pin Descriptions
Symbol
VF
X
IN1
VF
X
IN0
VF
X
IP1
VF
X
IP0
GS
X
1
GS
X
0
VF
R
OP1
VF
R
OP0
VF
R
ON1
VF
R
ON0
V
DD
Pin
17
4
16
5
15
6
20
1
19
2
8
Type
Name/Function
I
Voice Frequency Transmitter Negative Input.
Analog inverting input to the
uncommitted operational amplifier at the transmit filter input.
I
Voice Frequency Transmitter Positive Input.
Analog noninverting input to the
uncommitted operational amplifier at the transmit filter input.
O
Gain Set for Transmitter.
Output of the transmit uncommitted operational amplifi-
er. The pin is the input to the transmit differential filters.
O
Voice Frequency Receiver Positive Output.
This pin can drive 300
Ω
(or greater)
loads.
O
Voice Frequency Receiver Negative Output.
This pin can drive 300
Ω
(or great-
er) loads.
—
+5 V Power Supply
. This pin should be bypassed to analog ground with at least
0.1
µ
F of capacitance as close to the device as possible. V
DD
serves both analog
and digital internal circuits.
—
Analog Grounds
. Both ground pins must be connected on the circuit board. AGND
serves both analog and digital internal circuits.
I
Receive PCM Data Input
. The data on this pin is shifted into the device on the fall-
ing edges of MCLK. Sixteen consecutive bits of data (8 bits for channel 0, and
8 bits for channel 1) are entered after the FS pulse has been detected.
O
Transmit PCM Data Output
. This pin remains in the high-impedance state except
during active transmit time slots. Sixteen consecutive bits of data (8 bits for channel
0 and 8 bits for channel 1) are shifted out on the rising edge of MCLK. Data is shift-
ed out on the rising edge of MCLK.
I
Master Clock Input
. The frequency must be 2.048 MHz or 4.096 MHz. This clock
serves as the bit clock for all PCM data transfer. A 40% to 60% duty cycle is re-
quired.
—
Digital Ground
. Ground connection for the digital circuitry.
Frame Sync
. This signal is an edge trigger and must be high for a minimum of one
I
d
*
MCLK cycle. This signal must be derived from MCLK. If FS is low for 500
µ
s while
MCLK remains active, then the device fully powers down. An internal pull-down de-
vice is included on FS.
O
Voltage Common Mode
. 2.4 Vdc.
GNDA1
GNDA0
D
R
18
3
12
D
X
11
MCLK
9
GNDD
FS
10
13
VCM0
VCM1
7
14
* I
d
indicates a pull-down device is included on this lead.
Lucent Technologies Inc.
3
T7503 Dual PCM Codec with Filters
Data Sheet
February 1998
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
Parameter
Storage Temperature Range
Power Supply Voltage
Voltage on Any Pin with Respect to Ground
Maximum Power Dissipation (package limit)
Symbol
T
stg
V
DD
—
P
D
Min
–55
—
–0.5
—
Max
150
6.5
0.5 + V
DD
600
Unit
°
C
V
V
mW
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid
exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics
Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and
protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the
model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500
Ω
,
capacitance = 100 pF) is widely used and therefore can be used for comparison purposes. The HBM ESD
threshold presented here was obtained by using these circuit parameters:
HBM ESD Threshold Voltage
Device
Rating
T7503
>2000 V
Electrical Characteristics
Specifications apply for T
A
= –40
°
C to +85
°
C, V
DD
= 5 V
±
5%, MCLK = either 2.048 MHz or 4.096 MHz, and
GND = 0 V, unless otherwise noted.
dc Characteristics
Table 2. Digital Interface
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Current Pins Without Pull-
down
Input Current Pin with Pull-down
Output Current in High-impedance
State
Input Capacitance
Symbol
V
IL
V
IH
V
OL
V
OH
I
I
I
I
I
OZ
C
I
Test Conditions
All digital inputs
All digital inputs
D
X
, I
L
= 3.2 mA
D
X
, I
L
= –3.2 mA
D
X
, I
L
= –320
µ
A
Any digital input GND < V
IN
< V
DD
Any digital input GND < V
IN
< V
DD
D
X
—
Min
—
2.0
—
2.4
3.5
–10
2
–30
—
Typ
—
—
—
—
—
±
0.01
10
±
0.02
—
Max
0.8
—
0.4
—
—
10
150
30
5
Unit
V
V
V
V
V
µ
A
µ
A
µ
A
pF
4
Lucent Technologies Inc.
Data Sheet
February 1998
T7503 Dual PCM Codec with Filters
Electrical Characteristics
(continued)
dc Characteristics
(continued)
Table 3. Power Dissipation
Power measurements are made at MCLK = 4.096 MHz, outputs unloaded.
Parameter
Powerdown Current
Powerup Current
Symbol
I
DDO
I
DDU
Test Conditions
MCLK present and FS
≤
0.4 V
MCLK, FS pulse present
Min
—
—
Typ
0.1
18
Max
1
25
Unit
mA
mA
Transmission Characteristics
Table 4. Analog Interface
Parameter
Input Resistance, FS
X
I
Input Leakage Current, VF
X
I
Input Capacitance, VF
X
IN, VF
X
IP
Input Offset Voltage of Uncommitted
Op Amp, VF
X
IN – VF
X
IP
Input Common-mode Voltage Range,
VF
X
IN, VF
X
IP
Input Common-mode Rejection Ratio,
VF
X
IN, VF
X
IP
Gain Bandwidth Product (10 kHz) of Un-
committed Op Amp
Equivalent Input Noise Between VF
X
IN
and VF
X
IP at GS
X
Output Voltage Range, GS
X
dc Open-loop Voltage Gain, GS
X
Differential Output dc Offset Voltage
Load Capacitance, GS
X
Load Resistance, GS
X
VCM Output Voltage Referenced to GND
VCM Output Load Capacitance
Load Resistance, V
CM
Load Resistance, VF
R
O
Load Capacitance, VF
R
O
Output Resistance, VF
R
O
Output Voltage, VF
R
O
Output Leakage Current, VF
R
O, Power-
down
Output Voltage Swing, VF
R
O
Symbol
R
VFXI
I
BVFXI
—
—
—
—
—
—
Test Conditions
VFxI = 2.4 V
VFxI = 2.4 V
—
—
—
—
—
—
Min
1.0
–2.4
–5
1.2
—
—
—
0.5
90
–80
—
10
2.25
0
10
300
—
—
2.25
–30
3.2
Typ
—
±0.01
—
—
—
60
3000
–30
—
—
±10
—
—
2.35
—
—
—
—
0.3
2.35
±0.02
—
Max
—
2.4
10
5
V
DD
– 1.75
—
—
—
V
DD
– 0.5
—
80
50
—
2.5
50
—
—
100
3
2.5
30
—
Unit
MΩ
µA
pF
mV
V
dB
kHz
dBrnC
V
dB
mV
pF
kΩ
V
pF
kΩ
Ω
pF
Ω
V
µA
Vp-p
—
—
A
VOL
—
—
—
CL
X1
—
RL
X1
—
—
—
—
—
RL
VCM
—
RL
VFRO
—
CL
VFRO
—
RO
VFRO
0 dBm0, 1020 Hz PCM
code applied to D
R
VO
R
Alternating
±
zero
µ-law
PCM code applied to D
R
IO
VFRO
—
V
SWR
RL = 300
Ω
Lucent Technologies Inc.
5
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