Freescale Semiconductor
Technical Data
DATA SHEET
MC100ES6220
Rev 4, 04/2005
Low Voltage Dual 1:10 Differential
Low Voltage Dual
Buffer
ECL/PECL Clock Fanout
1:10 Differential
MC100ES6220
ECL/PECL Clock Fanout Buffer
MC100ES6220
The MC100ES6220 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6220
supports various applications that require the distribution of precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low skew outputs and superior digital signal
characteristics. Target applications for this clock driver are high performance
clock distribution in computing, networking and telecommunication systems.
Features
•
•
•
•
•
•
•
•
•
•
•
Two independent 1:10 differential clock fanout buffers
130 ps maximum device skew
SiGe technology
Supports DC to 1 GHz operation of clock or data signals
ECL/PECL compatible differential clock outputs
ECL/PECL compatible differential clock inputs
Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply
Standard 52-lead LQFP package with exposed pad for enhanced thermal
characteristics
Supports industrial temperature range
Pin and function compatible to the MC100EP220
52-lead Pb-free Package Available
LOW VOLTAGE DUAL
1:10 DIFFERENTIAL ECL/PECL
CLOCK FANOUT BUFFER
TB SUFFIX
52-LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336A-01
Functional Description
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 1336A-01
The MC100ES6220 is designed for low skew clock distribution systems and
supports clock frequencies up to 1 GHz. The device consists of two independent
clock fanout buffers. The CLKA and CLKB inputs can be driven by ECL or PECL compatible signals. The input signal of each
clock buffer is distributed to 10 identical, differential ECL/PECL outputs. If V
BB
is connected to the CLKA or CLKB input and
bypassed to GND by a 10 nF capacitor, the MC100ES6220 can be driven by single-ended ECL/PECL signals utilizing the V
BB
bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6220 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6220 supports positive (PECL) and negative (ECL) supplies. The MC100ES6220 is pin and function compatible to the
MC100EP220.
IDT™
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
MC100ES6220
© Freescale Semiconductor, Inc., 2005. All
acquired by Integrated Device Technology, Inc
Freescale Timing Solutions Organization has been
rights reserved.
1
MC100ES6220
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
NETCOM
QB0
QB1
QB1
Fanout Buffer A
V
CC
CLKA
CLKA
QA0
QA0
QA1
QA1
V
CC
QA5
QA5
QA4
QA4
QA3
QA3
QA2
QA2
QA1
QA1
QA0
QA0
39 38 37 36 35 34 33 32 31 30 29 28 27
26
40
41
42
43
44
45
46
47
48
49
50
51
52
1
V
CC
2
CC
QA9
QB0
QA6
QA6
QA7
QA7
QA8
QA8
QA9
V
CC
QB2
QB2
QB3
QB3
QB4
QB4
QB5
QB5
QB6
QB6
QB7
QB7
V
CC
25
24
23
22
V
EE
QA8
QA8
QA9
QA9
QB0
QB0
QB1
QB1
MC100ES6220
21
20
19
18
17
16
15
Fanout Buffer B
V
CC
CLKB
CLKB
V
EE
QB8
QB8
QB9
QB9
3
V
EE
4
CLKA
5
6
7
CLKB
8
14
9 10 11 12 13
QB9
QB9
QB8
QB8
CLKA
V
BB
V
BB
Figure 1. MC100ES6220 Logic Diagram
Table 1. Pin Configuration
Pin
CLKA, CLKA
CLKB, CLKB
QA[0-9], QA[0-9]
QB[0-9], QB[0-9]
V
EE(1)
V
CC
V
BB
Input
Input
Output
Output
Supply
Supply
Output
DC
I/O
Type
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
Figure 2. 52-Lead Package Pinout
(Top View)
Function
Differential reference clock signal input for fanout buffer A
Differential reference clock signal input for fanout buffer B
Differential clock outputs of fanout buffer A
Differential clock outputs of fanout buffer B
Negative power supply
Positive power supply. All V
CC
pins must be connected to the positive
power supply for correct DC and AC operation.
Reference voltage output for single ended ECL and PECL operation
1. In ECL mode (negative power supply mode), V
EE
is either –3.3 V or –2.5 V and V
CC
is connected to GND (0 V). In PECL mode (positive
power supply mode), V
EE
is connected to GND (0 V) and V
CC
is either
+3.3
V or
+2.5
V. In both modes, the input and output levels are
referenced to the most positive supply (V
CC
).
MC100ES6220
IDT™
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
2
2
CLKB
V
EE
V
MC100ES6220
Advanced Clock Drivers Devices
Freescale Semiconductor
MC100ES6220
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
NETCOM
Table 2. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
T
FUNC
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
Functional Temperature Range
–65
T
A
=
–40
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.6
V
CC
+
0.3
V
CC
+
0.3
±20
±50
125
T
J
= +110
Unit
V
V
V
mA
mA
°C
°C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 3. General Specifications
Symbol
V
TT
MM
HBM
CDM
LU
C
IN
θ
JA
,θ
JC
,
θ
JB
T
J
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Latch-Up Immunity
Input Capacitance
Thermal Resistance (junction-to-ambient,
junction-to-board, junction-to-case)
Operating Junction Temperature
(2)
(continuous operation)
MTBF = 9.1 years
200
4000
2000
200
4.0
See
Table 8. Thermal Resistance
0
110
Min
Typ
V
CC
– 2
(1)
Max
Unit
V
V
V
V
mA
pF
°C/W
°C
Inputs
Condition
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase.
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are
specified up to 110°C junction temperature allowing the MC100ES6220 to be used in applications requiring industrial temperature range. It
is recommended that users of the MC100ES6220 employ thermal modeling analysis to assist in applying the junction temperature
specifications to their particular application.
IDT™
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
MC100ES6220
MC100ES6220
3
Advanced Clock Drivers Devices
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Freescale Semiconductor
3
MC100ES6220
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
NETCOM
Table 4. PECL DC Characteristics
(V
CC
= 2.5 V
±
5% or V
CC
= 3.3 V
±
5%, V
EE
= GND, T
J
= 0°C to +110°C)
Symbol
Characteristics
Differential Input Voltage
(1)
Differential Cross Point Voltage
(2)
Input Current
(1)
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL differential signals)
V
PP
V
CMR
I
IN
V
IH
V
IL
I
IN
V
OH
V
OL
I
EE(5)
V
BB
0.1
1.0
1.3
V
CC
– 0.3
±150
V
V
µA
Differential operation
Differential operation
V
IN
= V
IL
or V
IN
= V
IH
Clock Inputs (PECL single ended signals)
Input Voltage High
Input Voltage Low
Input Current
(3)
V
CC
– 1.165
V
CC
– 1.810
V
CC
– 0.880
V
CC
– 1.475
±150
V
V
µA
V
IN
= V
IL
or V
IN
= V
IH
I
OH
= –30 mA
(4)
I
OL
= –5 mA
(4)
V
EE
pins
I
BB
= 0.3 mA
PECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9)
Output High Voltage
Output Low Voltage
V
CC
– 1.1
V
CC
– 1.9
V
CC
– 1.005
V
CC
– 1.705
80
V
CC
– 1.42
V
CC
– 0.7
V
CC
– 1.4
130
V
CC
– 1.20
V
V
Supply current and V
BB
Maximum Quiescent Supply Current without
Output Termination Current
Output Reference Voltage
mA
V
1. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
2. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
3. Input have internal pullup/pulldown resistors which affect the input current.
4. Termination 50
Ω
to V
TT
.
5. I
CC
calculation: I
CC
= (number of differential output used) x (I
OH
+
I
OL
)
+
I
EE
I
CC
= (number of differential output used) x (V
OH
– V
TT
)
÷
R
load
+
(V
OL
– V
TT
)
÷R
load
+
I
EE
.
Table 5. ECL DC Characteristics
(V
EE
= –2.5 V
±
5% or V
EE
= –3.3 V
±
5%, V
CC
= GND, T
J
= 0°C to +110°C)
Symbol
Characteristics
Differential Input Voltage
(1)
Differential Cross Point Voltage
(2)
Input Current
(1)
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals)
V
PP
V
CMR
I
IN
V
IH
V
IL
I
IN
V
OH
V
OL
I
EE(5)
V
BB
0.1
V
EE
+
1.0
1.3
–0.3
±150
V
V
µA
Differential operation
Differential operation
V
IN
= V
IL
or V
IN
= V
IH
Clock Inputs (ECL single ended signals)
Input Voltage High
Input Voltage Low
Input Current
(3)
–1.165
–1.810
–0.880
–1.475
±150
V
V
µA
V
IN
= V
IL
or V
IN
= V
IH
I
OH
= –30 mA
(4)
I
OL
= –5 mA
(4)
V
EE
pins
I
BB
= 0.3 mA
ECL Clock Outputs (QA0–A9, QA0–A9, QB0–B9, QB0–B9)
Output High Voltage
Output Low Voltage
–1.1
–1.9
–1.005
–1.705
–0.7
–1.4
V
V
Supply Current and V
BB
Maximum Quiescent Supply Current without
Output Termination Current
Output Reference Voltage
–1.42
80
130
–1.20
mA
V
1. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
2. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
3. Input have internal pullup/pulldown resistors which affect the input current.
4. Termination 50
Ω
to V
TT
.
5. I
CC
calculation: I
CC
= (number of differential output used) x (I
OH
+
I
OL
)
+
I
EE
I
CC
= (number of differential output used) x (V
OH
– V
TT
)
÷
R
load
+
(V
OL
– V
TT
)
÷
R
load
+
I
EE
.
MC100ES6220
IDT™
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
4
4
MC100ES6220
Advanced Clock Drivers Devices
Freescale Semiconductor
MC100ES6220
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
NETCOM
Table 6. AC Characteristics
(ECL: V
EE
= –3.3 V
±
5% or V
EE
= –2.5 V
±
5%, V
CC
= GND) or
(PECL: V
CC
= 3.3 V
±
5% or V
CC
= 2.5 V
±
5%, V
EE
= GND, T
J
= 0°C to +110°C)
(1)
Symbol
V
PP
V
CMR
f
CLK
t
PD
V
O(P-P)
t
sk(O)
t
sk(PP)
t
JIT(CC)
t
SK(P)
DC
O
t
r
, t
f
Characteristics
Differential Input Voltage
(2)
(peak-to-peak)
Differential Input Crosspoint Voltage
(3)
Input Frequency
PECL
ECL
Min
0.3
1.1
V
EE
+
1.1
0
Typ
Max
1.3
V
CC
– 0.3
–0.3
1000
Unit
V
V
V
MHz
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals)
Differential
PECL/ECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9)
Propagation Delay CLKx to Qx0-9
Differential Output Voltage (peak-to-peak)
Output-to-Output Skew
Output-to-Output Skew (part-to-part)
Output Cycle-to-Cycle Jitter
Output Pulse Skew
(4)
Output Duty Cycle
Output Rise/Fall Time
f
REF
< 0.1 GHz
f
REF
< 1.0 GHz
49.65
46.5
50
50
50
RMS (1σ)
285
400
600
60
130
200
1
35
50.35
53.5
350
550
ps
mV
ps
ps
ps
ps
%
%
ps
DC
REF
= 50%
DC
REF
= 50%
20% to 80%
Differential
Differential
Differential
1. AC characteristics apply for parallel output termination of 50
Ω
to V
TT
.
2. V
PP
(AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including t
PD
and
device-to-device skew.
3. V
CMR
(AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the
V
CMR
(AC) range and the input swing lies within the V
PP
(AC) specification. Violation of V
CMR
(AC) or V
PP
(AC) impacts the device
propagation delay, device and part-to-part skew.
4. Output pulse skew is the absolute difference of the propagation delay times: | t
pLH
– t
pHL
|.
Differential Pulse
Generator
Z = 50
Ω
Z = 50
Ω
Z = 50
Ω
R
T
= 50
Ω
V
TT
DUT
MC100ES6220
R
T
= 50
Ω
V
TT
Figure 3. MC100ES6220 AC Test Reference
CLK
N
CLK
N
Q
X
Q
X
V
PP
= 0.8 V
V
CMR
= V
CC
– 1.3 V
t
PD
(CLK
N
to Q
X
)
Figure 4. MC100ES6220 AC Reference Measurement Waveform
IDT™
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
MC100ES6220
MC100ES6220
5
Advanced Clock Drivers Devices
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Freescale Semiconductor
5
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