PC8540
Integrated Processor
Datasheet
Features
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Embedded e500 Book E-compatible Core Available up to 833 MHz
– 32-bit, Dual-issue, Superscalar, Seven-stage Pipeline
– 1850 MIPS at 800 MHz (Est. Dhrystone 2.1)
– 32 KB L1 Data and 32 KB L1 Instruction Cache with Line Locking Support
– 256 KB On-chip L2 Cache with Direct Mapped Capability
– Enhanced Hardware and Software Debug Support
– Memory Management Unit (MMU)
– SIMD Extension with Single Precision Floating Point
Two TSECs Supporting 10/100/1000 Mbps Ethernet (IEEE
®
802.3, 802.3u, 802.3x,
802.3z, and 802.3 ac-compliant) with Two GMII/TBI/RGMII Interfaces
166 MHz, 64-bit, 2.5V I/O, DDR SDRAM Memory Controller with Full ECC Support
500 MHz, 8-bit, LVDS I/O, RapidIO Controller
133 MHz, 64-bit, 3.3V I/O, PCI-X 1.0a/PCI 2.2 Bus Controller
166 MHz, 32-bit, 3.3V I/O, Local Bus with Memory Controller
Integrated Four-channel DMA Controller
Interrupt Controller
IEEE 1149.1 JTAG Test Access Port
1.2V Core Voltage with 3.3V and 2.5V I/O
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Description
The PC8540 contains a PowerPC
®
processor core. The PC8540 integrates a processor that implements the PowerPC
architecture with system logic required for networking, storage, and general-purpose embedded applications. For func-
tional characteristics of the processor, refer to the PC8540 Integrated Processor Preliminary Reference Manual.
Screening/Quality/Packaging
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T
J
= –55°C, +125°C
T
J
= –40°C, +110°C
783-pin HiTCE Package
783-pin FC-PBGA Package
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e2v semiconductors SAS 2014
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PC8540
1. Overview
The following section provides a high-level overview of the PC8540 features.
Figure 1-1
shows the major
functional units within the PC8540.
Figure 1-1.
Block Diagram
256KB
L2-Cache/
SRAM
e500
0
Coherency
Module
DDR
SDRAM
ROM
SDRAM,
GPIO
IRQs
DDR SDRAM Controller
e500 Core
32 KB L1
I Cache
32 KB L1
D Cache
Local Bus Controller
Programmable
Interrupt Controller
Core Complex Bus
l
RapidIO Controller
OCeaN
MII
10/100
ENET
PCI/PCI-X Controller
4ch DMA Controller
Serial
DUART
TSEC
I
2
C
I
2
C
Controller
TSEC
10/100/1G
10/100/1G
/100/1G
RapidIO-8
16 Gb/s
PCI-X 64b
133 MHz
MII, GMII, TBI,
RTBI, RGMII
MII, GMII, TBI,
RTBI, RGMII
1.1
Key Features
The following lists an overview of the PC8540 feature set.
• High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches
can be locked entirely or on a per-line basis. Separate locking for instructions and data
– Memory Management Unit (MMU) especially designed for embedded applications
– Enhanced hardware and software debug support
• 256 Kbyte L2 cache/SRAM
– Can be configured as follows:
– Full cache mode (256-Kbyte cache)
– Full memory-mapped SRAM mode (256-Kbyte SRAM mapped as a single 256 Kbyte
block or two 128-Kbyte blocks)
– Half SRAM and half cache mode (128-Kbyte cache and 128-Kbyte memory-mapped
SRAM)
– Full ECC support on 64-bit boundary in both cache and SRAM modes
– Cache mode supports instruction caching, data caching, or both
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– External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing)
– Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
– Supports locking the entire cache or selected lines. Individual line locks are set and cleared
through Book E instructions or by externally mastered transactions
– Global locking and flash clearing done through writes to L2 configuration registers
– Instruction and data locks can be flash cleared separately
– Read and write buffering for internal bus accesses
– SRAM features include the following:
– I/O devices access SRAM regions by marking transactions as snoopable (global)
– Regions can reside at any aligned location in the memory map
– Byte accessible ECC is protected using read-modify-write transactions accesses for
smaller than cache-line accesses.
• Address Translation and Mapping Unit (ATMU)
– Eight local access windows define mapping within local 32-bit address space
– Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI/PCI-X
– Four inbound windows plus a default and configuration window on RapidIO
– Four outbound windows plus default translation for PCI
– Eight outbound windows plus default translation for RapidIO
• DDR memory controller
– Programmable timing supporting DDR-1 SDRAM
– 64-bit data interface, up to 333 MHz data rate
– Four banks of memory supported, each up to 1 Gbyte
– DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
– Full ECC support
– Page mode support (up to 16 simultaneous open pages)
– Contiguous or discontiguous memory mapping
– Read-modify-write support for RapidIO atomic increment, decrement, set, and clear
transactions
– Sleep mode support for self refresh SDRAM
– Supports auto refreshing
– On-the-fly power management using CKE signal
– Registered DIMM support
– Fast memory access via JTAG port
– 2.5V SSTL2 compatible I/O
• RapidIO interface unit
– 8-bit RapidIO I/O and messaging protocols
– Source-synchronous Double Data Rate (DDR) interfaces
– Supports small type systems (small domain, 8-bit device ID)
– Supports four priority levels (ordering within a level)
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– Reordering across priority levels
– Maximum data payload of 256 bytes per packet
– Packet pacing support at the physical layer
– CRC protection for packets
– Supports atomic operations increment, decrement, set, and clear
– LVDS signaling
• RapidIO–compliant message unit
– One inbound data message structure (inbox)
– One outbound data message structure (outbox)
– Supports chaining and direct modes in the outbox
– Support of up to 16 packets per message
– Support of up to 256 bytes per packet and up to 4 Kbytes of data per message
– Supports one inbound doorbell message structure
• Programmable Interrupt Controller (PIC)
– Programming model is compliant with the OpenPIC architecture
– Supports 16 programmable interrupt and processor task priority levels
– Supports 12 discrete external interrupts
– Supports 4 message interrupts with 32-bit messages
– Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
– Four global high resolution timers/counters that can generate interrupts
– Supports 22 other internal interrupt sources
– Supports fully nested interrupt delivery
– Interrupts can be routed to external pin for external processing
– Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
– Interrupt summary registers allow fast identification of interrupt source
• I
2
C Controller
– Two-wire interface
– Multiple master support
– Master or slave I
2
C mode support
– On-chip digital filtering rejects spikes on the bus
• Boot sequencer
– Optionally loads configuration data from serial ROM at reset via the
I
2
C interface
– Can be used to initialize configuration registers and/or memory
– Supports extended I
2
C addressing mode
– Data integrity checked with preamble signature and CRC
• DUART
– Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
– Programming model compatible with the original 16450 UART and the PC16550D
• 10/100 Fast Ethernet Controller (FEC)
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– Operates at 10 to 100 megabits per second (Mbps) as a device debug and maintenance port
• Local Bus Controller (LBC)
– Multiplexed 32-bit address and data operating at up to 166 MHz
– Eight chip selects support eight external slaves
– Up to eight-beat burst transfers
– The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
– Three protocol engines available on a per chip select basis:
– General Purpose Chip select Machine (GPCM)
– Three User Programmable Machines (UPMs)
– Dedicated single data rate SDRAM controller
– Parity support
– Default boot ROM chip select with configurable bus width (8-,16-, or 32-bit)
• Two three-speed (10/100/1Gb) Ethernet controllers (TSECs)
– Dual IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers
– Support for different Ethernet physical interfaces:
– 10/100/1Gb Mbps IEEE 802.3 GMII
– 10/100 Mbps IEEE 802.3 MII
– 10 Mbps IEEE 802.3 MII
– 1000 Mbps IEEE 802.3z TBI
– 10/100/1Gb Mbps RGMII/RTBI
– Full- and half-duplex support
– Buffer descriptors are backward compatible with PC8260 and PC860T 10/100 programming
models
– 9.6-Kbyte jumbo frame support
– RMON statistics support
– 2-Kbyte internal transmit and receive FIFOs
– MII management interface for control and status
– Programmable CRC generation and checking
– Ability to force allocation of header information and buffer descriptors into L2 cache.
• OCeaN switch fabric
– Four-port crossbar packet switch
– Reorders packets from a source based on priorities
– Reorders packets to bypass blocked packets
– Implements starvation avoidance algorithms
– Supports packets with payloads of up to 256 bytes
• Integrated DMA controller
– Four-channel controller
– All channels accessible by both the local and remote masters
– Extended DMA functions (advanced chaining and striding capability)
– Support for scatter and gather transfers
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