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M4A3-512/192-12AI

Description
EE PLD, 12ns, CMOS, PBGA256, BGA-256
CategoryProgrammable logic devices    Programmable logic   
File Size1MB,61 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Download Datasheet Parametric View All

M4A3-512/192-12AI Overview

EE PLD, 12ns, CMOS, PBGA256, BGA-256

M4A3-512/192-12AI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerLattice
Parts packaging codeBGA
package instructionBGA-256
Contacts256
Reach Compliance Codeunknow
maximum clock frequency52.6 MHz
JESD-30 codeS-PBGA-B256
length27 mm
Dedicated input times
Number of I/O lines192
Number of terminals256
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize0 DEDICATED INPUTS, 192 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Programmable logic typeEE PLD
propagation delay12 ns
Certification statusNot Qualified
Maximum seat height1.7 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width27 mm
MACH 4 CPLD Family
High Performance EE CMOS
Programmable Logic
FEATURES
x
High-performance, EE CMOS 3.3-V & 5-V CPLD families
x
Flexible architecture for rapid logic designs
I
MAC ncludes
H 4A
Adv
Fa
M4A
ance
Info mily
-32/
Prel 32 and
rmatio
imin
M4A
n
ary
Infor
-128
mati /64
on
x
x
x
x
x
x
x
x
— Excellent First-Time-Fit
TM
and refit feature
— SpeedLocking
TM
performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns t
PD
Commercial and 7.5ns t
PD
Industrial
— 182MHz f
CNT
32 to 512 macrocells; 32 to 768 registers
44 to 352 pins in PLCC, PQFP, TQFP, BGA, fpBGA or caBGA packages
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-Friendly
TM
inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Advanced EE CMOS process provides high-performance, cost-effective solutions
Supported by ispDesignEXPERT
TM
software for rapid logic development
— Supports HDL design methodologies with results optimized for MACH 4A
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Lattice/Vantis and third-party hardware programming support
— Lattice/VantisPRO
TM
(formerly known as MACHPRO
®
) software for in-system programmability
support on PCs and automated test equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication#
17466
Amendment/0
Rev:
K
Issue Date:
January 2000
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