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I630-31FB8O2-155.520

Description
5 mm x 7 mm Ceramic Package SMD VCXO, LVCMOS / LVPECL / LVDS
File Size48KB,3 Pages
ManufacturerILSI
Websitehttp://www.ilsiamerica.com
Download Datasheet View All

I630-31FB8O2-155.520 Overview

5 mm x 7 mm Ceramic Package SMD VCXO, LVCMOS / LVPECL / LVDS

5 mm x 7 mm Ceramic Package SMD VCXO, LVCMOS / LVPECL / LVDS
Product Features
Small Surface Mount Package
Fast Sample Delivery
Frequencies to 1500 MHz
Pb Free/ RoHS Compliant
Leadfree Processing
I630 - Series
Applications
xDSL
Broadcast video
Wireless Base Stations
Sonet /SDH
WiMAX/WLAN
Server and Storage
Ethernet/LAN/WAN
Optical modules
Clock and data recovery
FPGA/ASIC
Backplanes
GPON
5.0
0.2
Frequency
LVCMOS
LVPECL
LVDS
Output Level
LVCMOS
LVPECL
LVDS
Duty Cycle
LVCMOS
LVPECL
LVDS
Rise / Fall Time
LVCMOS
LVPECL
LVDS
Output Load
LVCMOS
LVPECL
LVDS
Frequency Stability
Supply Voltage
Current
Linearity
Pullability
Control Voltage
Input Impedance
Phase Jitter (RMS)
At 12kHz to 20 MHz
Operating Temp.
Range
Storage
7.0 0.3
10 MHz to 225 MHz
10 MHz to 1500 MHz
10 MHz to 1500 MHz
1.9 Max.
VOH=90% VDD min., VOL=10 % VDD max.
VOH=VDD-1.03V max. (Nom. Load), VOL=VDD-1.6V max. (Nom. Load)
VOD=(Diff. Output) 350mV Typ.
50% ±5% @ 50%VDD
50% ±5% @ 50%*
50% ±5% @ 50%*
3.0 ns max. (90%/10%)*
0.6 ns max. (80%/20%)*
0.6 ns max. (80%/20%)*
Recommended Pad Layout
5.08
15pF
50
to VDD - 2.0 VDC
RL=100
/CL=10pF
See Table Below
3.3 VDC ± 10%, 2.5 VDC ± 5%
LVCMOS = 25 mA max., LVPECL = 60 mA max. LVDS = 35 mA max.
10% max.
See Table Below
1.65 VDC ± 1.65 VDC @ 3.3V
1.25 VDC ± 1.25 VDC @ 2.5V
50K
min.
0.9 ps typical
See Table Below
-40
C to +100
C
2.0
5.08
4.2
1.9
Pin Connection
1
Voltage Control
2
Enable/Disable or N/C
3
GND
4
Output
5
Output or N/C
6
V
DD
Dimension Units: mm
Part Number Guide
Package
Input
Voltage
3 = 3.3V
6 = 2.5V
Sample Part Number:
Stability
(in ppm)
F =
20
A =
25
B =
50
I630–31AB9H2–155.520
Enable / Disable
(Pin 2)
K = Enable
O = N/C
Operating
Temperature
1 = 0 C to +70 C
3 = -20 C to +70 C
2 = -40 C to +85 C
Pullabilty
B =
50
C =
100
Output
3 = LVCMOS
8 = LVDS
9 = LVPECL
Complimentary
Ouput (Pin 5) **
1 = N.C.
2 = Output
Frequency
I630
-155.520 MHz
NOTE: A 0.01 µF bypass capacitor is recommended between V
DD
(pin 6) and GND (pin 3) to minimize power supply noise. * Measured as percent of
waveform. ** Available on LVDS and LVPECL ouput only
.
ILSI
America
Phone: 775-851-8880 • Fax: 775-851-8882• e-mail: e-mail@ilsiamerica.com • www.ilsiamerica.com
10/17/12_E
Specifications subject to change without notice
Page 1
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