Lead-
Free
Package
Options
Available!
ispLSI 1016E
®
In-System Programmable High Density PLD
Functional Block Diagram
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— High-Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH-PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 125 MHz Maximum Operating Frequency
—
t
pd
= 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
Output Routing Pool
A2
A3
A4
A5
A6
A7
Array
D
Global Routing Pool (GRP)
EW
ES
IG
D Q
Logic
D Q
B5
B4
B3
B2
B1
B0
GLB
D Q
CLK
— Reprogram Soldered Device for Faster Prototyping
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
01
6E
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
The ispLSI 1016E is a High Density Programmable Logic
Device containing 96 Registers, 32 Universal I/O pins,
four Dedicated Input pins, three Dedicated Clock Input
pins, one Global OE input pin and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1016E offers
5V non-volatile in-system programmability of the logic, as
well as the interconnect to provide truly reconfigurable
systems. A functional superset of the ispLSI 1016
architecture, the ispLSI 1016E device adds a new global
output enable pin.
The basic unit of logic on the ispLSI 1016E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1...B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 1016E device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinatorial
or registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
U
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
SE
is
p
LS
I1
A
FO
R
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Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2006
1016e_09
1
Output Routing Pool
N
0139C1-isp
A1
D Q
B6
S
A0
B7
Specifications
ispLSI 1016E
Functional Block Diagram
Figure 1. ispLSI 1016E Functional Block Diagram
GOE 0/IN 3
MODE/IN 2
B7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
SDO/IN 1
A0
A1
B6
B5
B4
B3
B2
B1
B0
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
Output Routing Pool (ORP)
Input Bus
A4
A5
A6
A7
FO
R
N
EW
A3
Global
Routing
Pool
(GRP)
Clock
Distribution
Network
Megablock
ispEN
6E
A
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
LS
I1
01
*Note: Y1 and
RESET
are multiplexed on the same pin
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORP. Each ispLSI
1016E device contains two Megablocks.
U
SE
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source
4 mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
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The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1016E device are selected using the
Clock Distribution Network. Three dedicated clock pins
(Y0, Y1 and Y2) are brought into the distribution network,
and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0
and IOCLK 1) are provided to route clocks to the GLBs
and I/O cells. The Clock Distribution Network can also be
driven from a special clock GLB (B0 on the ispLSI 1016E
device). The logic of this GLB allows the user to create an
internal clock from a combination of internal signals
within the device.
2
Y0
Y1/RESET*
SCLK/Y2
0139B(1a)-isp
lnput Bus
A2
Output Routing Pool (ORP)
D
ES
IG
N
Generic
Logic Blocks
(GLBs)
S
Specifications
ispLSI 1016E
Absolute Maximum Ratings
1
Supply Voltage V
CC
................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
EW
D
ES
IG
MIN.
4.75
4.5
0
2.0
MAX.
5.25
5.5
0.8
V
cc
+1
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
N
UNITS
V
V
V
V
Table 2-0005/1016E
Case Temp. with Power Applied .............. -55 to 125°C
V
CC
V
IL
V
IH
T
A
= 0°C to + 70°C
Capacitance (T
A
=25
o
C, f=1.0 MHz)
SYMBOL
PARAMETER
A
FO
R
N
T
A
= -40°C to + 85°C
TYPICAL
8
12
UNITS
pf
pf
TEST CONDITIONS
V
CC
= 5.0V, V
PIN
= 2.0V
V
CC
= 5.0V, V
PIN
= 2.0V
Table 2-0006/1016E
PARAMETER
Data Retention
Erase/Reprogram Cycles
LS
I1
Data Retention Specifications
01
C
2
Y0 Clock Capacitance
6E
C
1
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)
MINIMUM
20
10000
MAXIMUM
–
–
UNITS
Years
Cycles
Table 2-0008/1016E
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Specifications
ispLSI 1016E
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
-125
-100, -80
1.5V
1.5V
See Figure 2
Table 2-0003/1016E
Figure 2. Test Load
≤
2 ns
≤
3 ns
+ 5V
R1
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
470Ω
∞
470Ω
∞
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
*
CL includes Test Fixture and Probe Capacitance.
0213a
DC Electrical Characteristics
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
Over Recommended Operating Conditions
FO
R
Table 2-0004/1016E
N
C
EW
I/O Active Pull-Up Current
LS
I1
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2, 4
A
CONDITION
6E
I
OL
= 8 mA
I
OH
= -4 mA
0V
≤
V
IN
≤
V
IL
(Max.)
3.5V
≤
V
IN
≤
V
CC
0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.5V, V
IH
= 3.0V
f
CLOCK
= 1 MHz
Commercial
Industrial
D
ES
IG
R2
CL
*
MIN.
–
2.4
–
–
–
–
–
–
–
TYP.
–
–
–
–
–
–
–
90
90
3
N
0.4
–
-10
10
-150
-150
-200
–
–
Device
Output
MAX. UNITS
V
V
μA
μA
μA
μA
mA
mA
mA
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
Output Short Circuit Current
Operating Power Supply Current
is
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01
Input or I/O Low Leakage Current
Table 2-0007/1016E
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1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25°C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate
maximum I
CC
.
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Test
Point
Specifications
ispLSI 1016E
External Timing Parameters
Over Recommended Operating Conditions
TEST
2
PARAMETER
#
COND.
4
DESCRIPTION
1
-125
–
–
125
1
-100
–
–
100
77.0
125
7.0
–
0.0
8.0
–
0.0
–
6.5
–
–
–
–
4.0
4.0
3.5
0.0
10.0
13.0
–
–
–
–
–
–
-80
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15.0
18.5
–
–
–
–
–
–
17.0
–
20.0
20.0
10.5
10.5
–
–
–
–
–
MIN. MAX. MIN. MAX. MIN. MAX.
7.5
10.0
–
–
–
–
4.5
–
–
5.5
–
–
6E
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
t
su3
t
h3
1.
2.
3.
4.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
–
–
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
2 Data Prop. Delay, Worst Case Path
3 Clk. Frequency with Int. Feedback
3
4 Clk. Frequency with Ext. Feedback
(
tsu2 + tco1
)
5 Clk. Frequency, Max. Toggle
(
1
twh + tw1
84.0
57.0
100
8.5
–
100
167
5.0
–
0.0
5.5
–
0.0
–
6 GLB Reg. Setup Time before Clk., 4 PT Bypass
7 GLB Reg. Clk. to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clk., 4 PT Bypass
9 GLB Reg. Setup Time before Clk.
10 GLB Reg. Clk. to Output Delay
11 GLB Reg. Hold Time after Clk.
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
EW
10.0
12.0
12.0
7.0
7.0
–
–
–
–
N
5.0
–
–
–
–
R
FO
18 Ext. Sync. Clk. Pulse Duration, High
3.0
3.0
0.0
A
19 Ext. Sync. Clk. Pulse Duration, Low
21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3)
20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0
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LS
I1
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions Section.
01
5
D
ES
IG
5.0
–
–
–
13.5
–
0.0
–
9.5
6.0
0.0
–
10.0
–
15.0
15.0
9.0
9.0
–
–
–
–
–
–
–
5.0
5.0
4.5
0.0
)
Table 2-0030-16/125,100, 80
N
8.0
9.5
S
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