PR E LI MIN ARY
LM3S601 Microcontroller
DATA SHEE T
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2
Preliminary
October 01, 2007
LM3S601 Microcontroller
Table of Contents
About This Document .................................................................................................................... 18
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
18
18
18
18
20
25
25
26
27
27
28
29
30
30
31
32
33
35
35
35
36
36
36
36
36
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.9
Architectural Overview ...................................................................................................... 20
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
System Block Diagram ..............................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 34
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 40
Interrupts ............................................................................................................................ 42
JTAG Interface .................................................................................................................... 44
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
45
45
46
47
48
48
49
50
50
52
6
6.1
6.1.1
System Control ................................................................................................................... 54
Functional Description ............................................................................................................... 54
Device Identification .................................................................................................................. 54
October 01, 2007
Preliminary
3
Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Reset Control ............................................................................................................................
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
54
57
57
60
60
61
62
7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
7.6
Internal Memory ............................................................................................................... 113
Block Diagram ........................................................................................................................ 113
Functional Description ............................................................................................................. 113
SRAM Memory ........................................................................................................................ 113
Flash Memory ......................................................................................................................... 114
Flash Memory Initialization and Configuration ........................................................................... 116
Changing Flash Protection Bits ................................................................................................ 116
Flash Programming ................................................................................................................. 117
Register Map .......................................................................................................................... 117
Flash Register Descriptions (Flash Control Offset) ..................................................................... 118
Flash Register Descriptions (System Control Offset) .................................................................. 125
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3
8.4
8.5
General-Purpose Input/Outputs (GPIOs) ....................................................................... 129
Block Diagram ........................................................................................................................ 130
Functional Description ............................................................................................................. 130
Data Control ........................................................................................................................... 131
Interrupt Control ...................................................................................................................... 132
Mode Control .......................................................................................................................... 133
Pad Control ............................................................................................................................. 133
Identification ........................................................................................................................... 133
Initialization and Configuration ................................................................................................. 133
Register Map .......................................................................................................................... 134
Register Descriptions .............................................................................................................. 136
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers ................................................................................................. 168
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
169
169
169
169
171
175
175
176
176
177
177
178
178
179
10
10.1
10.2
Watchdog Timer ............................................................................................................... 204
Block Diagram ........................................................................................................................ 204
Functional Description ............................................................................................................. 204
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October 01, 2007
LM3S601 Microcontroller
10.3
10.4
10.5
Initialization and Configuration ................................................................................................. 205
Register Map .......................................................................................................................... 205
Register Descriptions .............................................................................................................. 206
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.4
11.5
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 227
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Bit Rate Generation .................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Frame Formats .......................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
I
2
C Bus Functional Overview ....................................................................................................
Available Speed Modes ...........................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
Command Sequence Flow Charts ............................................................................................
Initialization and Configuration .................................................................................................
I
2
C Register Map .....................................................................................................................
Register Descriptions (I
2
C Master) ...........................................................................................
Register Descriptions (I2C Slave) .............................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Internal Reference Programming ..............................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
228
228
228
229
230
230
230
231
231
232
233
265
265
266
266
266
267
274
275
276
302
302
303
305
306
306
307
313
314
315
328
338
338
340
341
341
342
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.3
12.4
12.5
Synchronous Serial Interface (SSI) ................................................................................ 265
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.3
13.4
13.5
13.6
Inter-Integrated Circuit (I
2
C) Interface ............................................................................ 302
14
14.1
14.2
14.2.1
14.3
14.4
14.5
Analog Comparators ....................................................................................................... 337
15
15.1
15.2
Pulse Width Modulator (PWM) ........................................................................................ 350
Block Diagram ........................................................................................................................ 350
Functional Description ............................................................................................................. 350
October 01, 2007
Preliminary
5
PCB Design
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