PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
FEATURES
•
•
•
•
•
•
19MHz to 65MHz crystal input.
Output range: 9.5MHz – 65MHz
Selectable OE Logic (enable high or enable low).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Supports 2.5V or 3.3V Power Supply.
Available in die form.
DIE CONFIGURATION
OUTSEL0^
65 mil
OUTSEL1^
Reserved
VDD
VDD
VDD
VDD
N/C
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OE_SEL^
XIN
XOUT
N/C
62 mil
26
27
Die ID:
A2020-20B
15
28
14
DESCRIPTION
The PLL620-80 is a XO IC specifically designed to
work with fundamental or 3
rd
OT crystals between
19MHz and 65MHz. The selectable divide by two
feature extends the operation range from 9.5MHz to
65MHz. It requires very low current into the crystal
resulting in better overall stability. The OE logic
feature allows selection of enable high or enable low.
Furthermore, it provides selectable CMOS, PECL or
LVDS outputs.
S2^
OE
CTRL
N/C
13
29
12
11
30
C502A
31
1
2
3
4
5
6
7
8
10
9
Reserved
Y
(0,0)
X
OUTPUT SELECTION AND ENABLE
OUT_SEL1*
(Pad 18)
0
0
1
1
OE_SELECT
(Pad 9)
0
1 (Default)
OUT_SEL0*
(Pad 25)
0
1
0
1
OE_CTRL
(Pad 30)
0
1 (Default)
0 (Default)
1
Selected Output*
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
State
Tri-state
Output enabled
Output enabled
Tri-state
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
OE
Q
XIN
XOUT
Oscillator
Amplifier
Q
S2
PLL620-80
Pads #9, #18 & #25: Bond to GND to set to “0”,
No connection results to “default” setting
through internal pull-up.
OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1”
Logical states defined by CMOS levels if OE_SELECT is “0”
OUTPUT FREQUENCY SELECTOR
S2
0
1(Default)*
*Internally set to ‘Default’ through 60K
Output
Input/2
Input
pull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 1
GNDBUF
GNDBUF
GND
GND
GND
GND
GND
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Interelectrode Capacitance
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0
R
E
CONDITIONS
Fundamental
Die
AT cut
MIN.
19
TYP.
8*
MAX.
65
5
30
UNITS
MHz
pF
pF
Ω
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific
limits.
3. General Electrical Specifications
PARAMETERS
Supply Current (Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS/CMOS
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
MIN.
2.97
45
45
45
TYP.
MAX.
100/80/40
3.63
55
55
55
UNITS
mA
V
%
mA
50
50
50
±50
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 2
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
4. Jitter Specifications
PARAMETERS
Period jitter RMS at 27MHz
Period jitter peak-to-peak at 27MHz
Accumulated jitter RMS at 27MHz
Accumulated jitter peak-to-peak at 27MHz
Random Jitter
Measured on Wavecrest SIA 3000
CONDITIONS
With capacitive decoupling between
VDD and GND. Over 10,000 cycles
With capacitive decoupling between
VDD and GND. Over 1,000,000
cycles.
“RJ” measured on Wavecrest SIA
3000
MIN.
TYP.
2.3
18.5
2.3
24
2.3
MAX.
20
25
UNITS
ps
ps
ps
5. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
27MHz
@10Hz
-75
@100Hz
-100
@1kHz
-125
@10kHz
-140
@100kHz
-145
UNITS
dBc/Hz
Note: Phase Noise measured on Agilent E5500
6. CMOS Output Electrical Specifications
PARAMETERS
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
SYMBOL
I
OH
I
OL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
MIN.
30
30
10
10
TYP.
MAX.
UNITS
mA
mA
mA
mA
2.4
1.2
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 3
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
7. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
V
out
= V
DD
or GND
V
DD
= 0V
8. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
C
L
= 10pF
50Ω
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 4
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
9. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
V
OH
V
OL
CONDITIONS
R
L
= 50
Ω
to (V
DD
– 2V)
(see figure)
MIN.
V
DD
– 1.025
MAX.
V
DD
– 1.620
UNITS
V
V
10. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
t
r
t
f
PECL Levels Test Circuit
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
TYP.
0.6
0.5
MAX.
1.5
1.5
UNITS
ns
ns
PECL Output Skew
VDD
OUT
OUT
50Ω
2.0V
50%
50Ω
OUT
OUT
t
SKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 5
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