converters with a high speed serial interface. They are
designed for digitizing high frequency, wide dynamic
range signals with an input bandwidth of 700MHz. The
input range of the ADC can be optimized using the PGA
front end. The output data is serialized according to the
JEDEC serial interface for data converters specification
(JESD204).
The LTC2273/LTC2272 are perfect for demanding applica-
tions where it is desirable to isolate the sensitive analog
circuits from the noisy digital logic. The AC performance
includes a 77.7dB Noise Floor and 100dB spurious free
dynamic range (SFDR). Ultra low internal jitter of 80fs
RMS allows undersampling of high input frequencies
with excellent noise performance. Maximum DC specs
include ±4.5LSB INL and ±1LSB DNL (no missing codes)
over temperature.
The encode clock inputs, ENC
+
and ENC
–
, may be driven
differentially or single-ended with a sine wave, PECL,
LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer
allows high performance at full speed with a wide range
of clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
High Speed Serial Interface (JESD204)
Sample Rate: 80Msps/65Msps
77.7dBFS Noise Floor
100dB SFDR
SFDR >90dB at 140MHz (1.5V
P-P
Input Range)
PGA Front End (2.25V
P-P
or 1.5V
P-P
Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Single 3.3V Supply
Power Dissipation: 1100mW/990mW
Clock Duty Cycle Stabilizer
Pin Compatible Family
105Msps: LTC2274
80Msps: LTC2273
65Msps: LTC2272
40-Pin 6mm
×
6mm QFN Package
APPLICATIONS
n
n
n
n
n
n
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
TYPICAL APPLICATION
3.3V
SENSE
V
CM
1.25V
COMMON MODE
BIAS VOLTAGE
INTERNAL ADC
REFERENCE
GENERATOR
FAM
SYNC
+
8B/10B
ENCODER
16
20
SYNC
–
OV
DD
1.2V TO 3.3V
0.1μF
50Ω
A
IN +
ANALOG
INPUT
A
IN
–
ASIC OR FPGA
128k Point FFT, f
IN
= 4.93MHz,
–1dBFS, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
2.2μF
50Ω
AMPLITUDE (dBFS)
CMLOUT
+
+
SERIAL
RECEIVER
+
S/H
AMP
–
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
ENC
+
ENC
–
16-BIT
PIPELINED
ADC CORE
SERIALIZER
CORRECTION
LOGIC
CMLOUT
–
–
SCRAMBLER/
PATTERN
GENERATOR
PGA DITH MSBINV SHDN
20X
PLL
GND
V
DD
3.3V
0.1μF
0.1μF
22732 TA01
0
10
20
30
FREQUENCY (MHz)
40
22732
G04
PAT1 PAT0 SCRAM SRR1 SRR0
22732fa
1
LTC2273/LTC2272
ABSOLUTE MAXIMUM RATINGS
OV
DD
= V
DD
(Notes 1, 2)
PIN CONFIGURATION
TOP VIEW
MSBINV
SCRAM
SENSE
PAT1
PAT0
SHDN
GND
GND
FAM
30 GND
29 SYNC
–
28 SYNC
+
27 GND
41
26 GND
25 OV
DD
24 CMLOUT
+
23 CMLOUT
–
22 OV
DD
21 GND
11 12 13 14 15 16 17 18 19 20
V
DD
GND
V
DD
GND
SRR0
SRR1
ISMODE
SHDN
DITH
PGA
V
CM
40 39 38 37 36 35 34 33 32 31
V
DD
1
V
DD
2
GND 3
A
IN+
4
A
IN–
5
GND 6
GND 7
GND 8
ENC
+
9
ENC
–
10
Supply Voltage (V
DD
) ................................... –0.3V to 4V
Analog Input Voltage (Note 3) .......–0.3V to (V
DD
+ 0.3V)
Digital Input Voltage......................–0.3V to (V
DD
+ 0.3V)
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Power Dissipation .............................................2000mW
Operating Temperature Range
LTC2273C/LTC2272C ............................... 0°C to 70°C
LTC2273I/LTC2272I.............................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Digital Output Supply Voltage (OV
DD
) .......... –0.3V to 4V
UJ PACKAGE
40-LEAD (6mm 6mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 22°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2273CUJ#PBF
LTC2273IUJ#PBF
LTC2272CUJ#PBF
LTC2272IUJ#PBF
LEAD BASED FINISH
LTC2273CUJ
LTC2273IUJ
LTC2272CUJ
LTC2272IUJ
TAPE AND REEL
LTC2273CUJ#TRPBF
LTC2273IUJ#TRPBF
LTC2272CUJ#TRPBF
LTC2272IUJ#TRPBF
TAPE AND REEL
LTC2273CUJ#TR
LTC2273IUJ#TR
LTC2272CUJ#TR
LTC2272IUJ#TR
PART MARKING*
LTC2273UJ
LTC2273UJ
LTC2272UJ
LTC2272UJ
PART MARKING*
LTC2273UJ
LTC2273UJ
LTC2272UJ
LTC2272UJ
PACKAGE DESCRIPTION
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
PACKAGE DESCRIPTION
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
CONDITIONS
Differential Analog Input (Note 5) T
A
= 25°C
Differential Analog Input (Note 5)
Differential Analog Input
(Note 6)
External Reference
Internal Reference
External Reference
SYMBOL
Integral Linearity Error
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Drift
Gain Error
Full-Scale Drift
Transition Noise
MIN
l
l
l
l
TYP
±1.2
±1.5
±0.3
±1
±10
±0.2
±30
±15
3
MAX
±4
±4.5
±1
±8.5
±1.5
UNITS
LSB
LSB
LSB
mV
μV/°C
%FS
ppm/°C
ppm/°C
LSB
RMS
22732fa
2
LTC2273/LTC2272
ANALOG INPUT
SYMBOL
V
IN
V
IN, CM
I
IN
I
SENSE
C
IN
t
AP
t
JITTER
CMRR
BW-3dB
The
l
denotes denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. (Note 4)
PARAMETER
Analog Input Range (A
IN+
–
A
IN–
)
Analog Input Common Mode
Analog Input Leakage Current
SENSE Input Leakage Current
Analog Input Capacitance
Sample-and-Hold
Acquisition Delay Time
Sample-and-Hold
Acquisition Delay Time Jitter
Analog Input
Common Mode Rejection Ratio
Full Power Bandwidth
1V < (A
IN+
= A
IN–
) <1.5V
R
S
≤ 25Ω
CONDITIONS
3.135V ≤ V
DD
≤ 3.465V
Differential Input (Note 7)
0V ≤ A
IN+
,
A
IN–
≤ V
DD
(Note 10)
0V ≤ SENSE ≤ V
DD
(Note 11)
Sample Mode ENC
+
< ENC
–
Hold Mode ENC
+
> ENC
–
l
l
l
MIN
1
–1
–3
TYP
1.5 or 2.25
1.25
MAX
1.5
1
3
UNITS
V
P-P
V
μA
μA
pF
pF
ns
fs
RMS
dB
MHz
6.7
1.8
1
80
80
700
DYNAMIC ACCURACY
SYMBOL PARAMETER
SNR
Signal-to-Noise Ratio
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 4)
LTC2273
CONDITIONS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
15MHz Input (2.25V Range, PGA = 0), T
A
= 25°C
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1), T
A
= 25°C
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
SFDR
Spurious Free Dynamic
Range 2
nd
or 3
rd
Harmonic
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
15MHz Input (2.25V Range, PGA = 0), T
A
= 25°C
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1), T
A
= 25°C
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
l
l
LTC2272
MAX
MIN
TYP
77.6
75.4
76.5
76.2
77.5
77.2
75.3
77.2
75.1
74.8
76.3
74.5
75.9
74.3
100
100
85
84
95
95
100
86
94
92
85
90
80
85
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MIN
TYP
77.6
75.4
76.5
76.2
77.5
77.2
75.3
77.2
75.1
74.8
76.3
74.5
75.9
74.3
100
100
l
74.5
74.2
74.5
74.2
85
84
95
95
100
86
94
92
85
90
80
85
l
84
83
84
83
22732fa
3
LTC2273/LTC2272
DYNAMIC ACCURACY
SYMBOL PARAMETER
SFDR
Spurious Free Dynamic
Range 4
th
Harmonic or
Higher
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS unless otherwise noted. (Note 4)
LTC2273
CONDITIONS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
l
LTC2272
MAX
MIN
TYP
100
100
90
100
100
100
100
95
100
90
95
77.5
75.3
76.3
75.9
77.4
77
75.2
76.7
75
74.7
75.3
74.3
73.4
73.4
105
105
105
105
105
105
100
100
100
100
115
115
97
115
115
115
115
110
110
105
105
MAX
UNITS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
MIN
TYP
100
100
90
100
100
100
100
95
100
90
95
77.5
75.3
l
90
90
S/(N+D) Signal-to-Noise
Plus Distortion Ratio
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
15MHz Input (2.25V Range, PGA = 0), T
A
= 25°C
15MHz Input (2.25V Range, PGA = 0
15MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1), T
A
= 25°C
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
l
76.3
75.9
77.4
77
75.2
76.7
75
74.7
75.3
74.3
73.4
73.4
105
105
105
105
105
105
100
100
100
100
115
115
l
74.4
74.1
74.4
74.1
SFDR
Spurious Free Dynamic
Range at –25dBFS Dither
“OFF”
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
SFDR
Spurious Free Dynamic
Range at –25dBFS Dither
“ON”
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
l
97
115
115
115
115
110
110
105
105
22732fa
4
LTC2273/LTC2272
The
l
denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
PARAMETER
V
CM
Output Voltage
V
CM
Output Tempco
V
CM
Line Regulation
V
CM
Output Resistance
CONDITIONS
I
OUT
= 0
I
OUT
= 0
3.135V ≤ V
DD
≤ 3.465V
–1mA ≤ | I
OUT
| ≤ 1mA
l
l
l
COMMON MODE BIAS CHARACTERISTICS
MIN
1.15
TYP
1.25
40
1
2
MAX
1.35
UNITS
V
ppm/°C
mV/V
Ω
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL
V
ID
V
ICM
R
IN
C
IN
V
SID
V
SICM
R
SIN
C
SIN
V
IH
V
IL
I
IN
C
IN
V
OH
PARAMETER
Differential Input Voltage
Common Mode Input Voltage
Input Resistance
Input Capacitance
SYNC
Differential Input
Voltage
SYNC
Common Mode Input
Voltage
SYNC
Input Resistance
SYNC
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
Output High Level
Directly-Coupled 50Ω to OV
DD
Directly-Coupled 100Ω Differential
AC-Coupled
Directly-Coupled 50Ω to OV
DD
Directly-Coupled 100Ω Differential
AC-Coupled
Directly-Coupled 50Ω to OV
DD
Directly-Coupled 100Ω Differential
AC-Coupled
Single-Ended Differential
V
DD
= 3.3V
V
DD
= 3.3V
V
IN
= 0V to V
DD
(Note 7)
Internally Set
Externally Set (Note 7)
CONDITIONS
(Note 7)
Internally Set
Externally Set (Note 7)
(See Figure 2)
Encode Inputs (ENC
+
, ENC
–
)
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
For an RTL design, ISE place & route will generate an sdf file. If certain constraints are added to the RTL design before synthesis, will the generated sdf file change? Is there any relationship betwe...
[hide]The application of dimming technology will further reduce energy consumption and save electricity for lighting. At present, public lighting electricity accounts for one-third of the entire light...
[i=s]This post was last edited by littleshrimp on 2015-12-15 17:24[/i] I know that different designs may be required for different applications, and there is probably no definite answer. Recently, I w...
Actel Corporation of the United States recently announced the first four products of the FPGA series "Fusion" that mix analog circuits and flash memory, and will start shipping samples of one of them....
This thing has a long history, several decades old, but it is also the pride of amateur wireless enthusiasts:lolI've let it slip, guess what this is....
Once the province of a few experts with their own dedicated chipsets, RF circuit design techniques are now integrated with digital and analog circuit blocks on the same IC. Furthermore, the critical s...
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
