CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
SUPPLY
I
S
I
SD
ANALOG
V
OL
V
OH
I
SC
PSRR
t
D
V
AC
V
DROOP
R
INH
REG
BG
DIGITAL
V
IH
V
IL
F
CLK
t
S
t
H
t
LC
t
CE
t
DCO
R
SDIN
Supply Current
V
S
= 15V, V
SD
= 5V, V
REFH
= 13V, V
REFL
= 2V,
R
L
= 1.5k and
C
L
= 200pF to 0V, T
A
= 25°C, unless
otherwise specified.
CONDITIONS
MIN
TYP
MAX
UNIT
DESCRIPTION
No load
7.6
0.17
9
0.35
mA
mA
Digital Supply Current
Output Swing Low
Output Swing High
Short Circuit Current
Power Supply Rejection Ratio
Program to Out Delay
Accuracy
Droop Voltage
Input Resistance @ V
REFH
, V
REFL
Load Regulation
Band Gap
Sinking 5mA (V
REFH
= 15V, V
REFL
= 0)
Sourcing 5mA (V
REFH
= 15V, V
REFL
= 0)
R
L
= 10
V
S
+ is moved from 14V to 16V
14.85
100
45
50
14.95
140
60
4
20
1
34
150
mV
V
mA
dB
ms
mV
2
mV/ms
k
I
OUT
= 5mA step
1.1
0.5
1.3
1.5
1.6
mV/mA
V
Logic 1 Input Voltage
Logic 0 Input Voltage
Clock Frequency
Setup Time
Hold Time
Load to Clock Time
Clock to Load Line
Clock to Out Delay Time
S
DIN
Input Resistance
Negative edge of SCLK
V
SD
-
20%
20%*
V
SD
5
20
20
20
20
10
1
V
V
MHz
ns
ns
ns
ns
ns
G
FN7005 Rev 4.00
June 24, 2005
Page 2 of 12
EL5825
Pin Descriptions
24-PIN QFN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
24-PIN TSSOP
3
4
5
6
7
8
9
11
10
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
PIN NAME
OSC
VSD
NC
VS
REFH
REFL
GND
CAP
NC
NC
NC
OUTH
OUTG
OUTF
OUTE
GND
OUTD
OUTC
OUTB
OUTA
ENA
SDI
SCLK
SDO
Analog Output
Analog Output
Analog Output
Analog Output
Power
Analog Output
Analog Output
Analog Output
Analog Output
Logic Input
Logic Input
Logic Input
Logic Output
Power
Analog Input
Analog Input
Power
Analog
PIN TYPE
IP/OP
Power
PIN DESCRIPTION
Oscillator pin for synchronizing multiple chips
Positive power supply for digital circuits (3.3V - 5V)
Not connected
Positive supply voltage for analog circuits
High reference voltage
Low reference voltage
Ground
Decoupling capacitor for internal reference generator, 0.1µF
Not connected
Not connected
Not connected
Channel H programmable output voltage
Channel G programmable output voltage
Channel F programmable output voltage
Channel E programmable output voltage
Ground
Channel D programmable output voltage
Channel C programmable output voltage
Channel B programmable output voltage
Channel A programmable output voltage
Chip select, low enables data input to logic
Serial data input
Serial data clock
Serial data output
FN7005 Rev 4.00
June 24, 2005
Page 3 of 12
EL5825
Typical Performance Curves
0.3
0.2
0.1
I
SD
(nA)
0
-0.1
-0.2
-0.3
10
INPUT CODE
180
160
140
120
100
80
60
V
S
=15V
V
SD
=5V
V
REFH
=13V
V
REFL
=2V
210
410
610
810
1010
40
20
0
3
3.5
4
4.5
5
5.5
V
SD
(V)
DIFFERENTIAL NONLINEARITY (LSB)
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. DIGITAL SUPPLY CURRENT vs DIGITAL SUPPLY
VOLTAGE
7.2
7
6.8
6.6
I
S
(mA)
6.4
6.2
6
5.8
5.6
4
6
8
V
OUT
=0V
V
S
(V)
0mA
5mA
V
S
=V
REFH
=15V
M=400ns/DIV
5mA/DIV
C
L
=4.7nF
R
S
=20
5V
C
L
=1nF
R
S
=20
C
L
=180pF
10
12
14
16
18
200mV/DIV
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 4. TRANSIENT LOAD REGULATION (SOURCING)
V
S
=V
REFH
=15V
M=400ns/DIV
M=200µs/DIV
5mA
0mA
C
L
=1nF
R
S
=20
SCLK
SDA
ENA
C
L
=4.7nF
R
S
=20
C
L
=180pF
OUTA
FIGURE 5. TRANSIENT LOAD REGULATION (SINKING)
FIGURE 6. LARGE SIGNAL RESPONSE (RISING FROM 0V
TO 8V)
FN7005 Rev 4.00
June 24, 2005
Page 4 of 12
EL5825
Typical Performance Curves
(Continued)
M=200µs/div
SCLK
SDA
ENA
OUTA
FIGURE 7. SMALL SIGNAL RESPONSE (FALLING FROM 200mV TO 100mV)
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