[EXT]. All specifications –40 C to +105 C unless otherwise noted.)
Test Conditions/Comments
f
IN
= 30 kHz Any Channel, f
SAMPLE
= 350 kHz
V
REF
Internal or External
fa = 29 kHz, fb = 30 kHz
Unit
dB min
dB max
dB typ
dB max
dB max
dB typ
Bits
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
V min
V max
µA
max
pF max
V min
V max
µA
max
pF max
f
IN
= 20 kHz
Any Channel
Nominal 2.5 V
% max
ppm/°C typ
V min
V max
V min
V max
µA
max
pF max
V
DD
= 5 V
±
10%
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
V
DD
= 3 V
±
10%
Typically 10 nA, V
IN
= 0 V to V
DD
V min
V min
V max
µA
max
pF max
µs
max
ns max
I
SOURCE
= 200
µA
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
I
SINK
= 200
µA
–2–
REV.
C
B
AD7811/AD7812
Parameter
POWER SUPPLY
V
DD
I
DD
Normal Operation
Power-Down
Full Power-Down
Partial Power-Down (Internal Ref)
Power Dissipation
Normal Operation
Auto Full Power-Down
Throughput 1 kSPS
Throughput 10 kSPS
Throughput 100 kSPS
Partial Power-Down (Internal Ref)
Full Power-Down
Y Version
2.7
5.5
3.5
1
350
10.5
31.5
315
3.15
1.05
3
Unit
V min
V max
mA max
µA
max
µA
max
mW max
See Power vs. Throughput Section
µW
max
µW
max
mW max
mW max
µW
max
Test Conditions/Comments
For Specified Performance
Digital Inputs = 0 V or V
DD
See Power-Up Times Section
V
DD
= 3 V
NOTES
1
See Terminology.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2
(V
Parameter
t
POWER-UP
t
1
t
2
t
3
t
4
t
5 3
t
6 3
t
7 3
t
8
t
9
t
103, 4
t
11
Y Version
1.5
2.3
20
25
25
5
5
10
10
5
20
100
Unit
DD
= 2.7 V to 5.5 V, V
REF
= V
DD
[EXT] unless otherwise noted)
Conditions/Comments
Power-Up Time of AD7811/AD7812 after Rising Edge of
CONVST
Conversion Time
CONVST
Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
RFS Rising Edge to SCLK Rising Edge Setup Time
TFS Falling Edge to SCLK Falling Edge Setup Time
SCLK Rising Edge to Data Out Valid
DIN Data Valid to SCLK Falling Edge Setup Time
DIN Data Valid after SCLK Falling Edge Hold Time
SCLK Rising Edge to D
OUT
High Impedance
DOUT High Impedance to
CONVST
Falling Edge
µs
(max)
µs
(max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (min)
ns (max)
ns (min)
NOTES
1
Sample tested to ensure compliance.
2
See Figures 16, 17 and 18.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD
= 5 V
±
10% and
0.4 V or 2 V for V
DD
= 3 V
±
10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
11
, quoted in the Timing Characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
200 A
I
OL
TO
OUTPUT
PIN
2.1V
C
L
50pF
200 A
I
OH
Figure 1. Load Circuit for Digital Output Timing Specifications
REV.
C
–3–
AD7811/AD7812
ABSOLUTE MAXIMUM RATINGS*
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to DGND (CONVST, SCLK, RFS, TFS,
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