-..
W
I
ANALOG
DEVICES
HighResolution
16-Bit0/A Converters
ADoAC71/Ao
DAC72*
FEATURES
16-Bit Resolution
j: 0.003% Maximum Nonlinearity
Low Gain Drift j: 7ppm/oC
0 to + 70°C Operation (AD DAC71, AD DAC71H,
AD DAC72C)
-
25°C to +
85°C
Operation (AD DAC72)
Current and Voltage Models Available
Improved Second-Source
Low Cost
AD DAC71/AD DAC 72 FUNCTIONAL
BLOCK DIAGRAM
.
if1
SUMMING JUNCTION
BIT 9
OBS
PRODUCT DESCRIPTION
The AD DAC71 and AD DACn are high resolution 16-bit
hybrid IC digital-to-analog converters including reference, scaling
resistors and output amplifier (V models).
The devices offer outstanding accuracy, including maximum
linearity error of 0.003% at room temperature and maximum
gain drifts of 15ppmrC (AD DAC71, AD DAC7IH, AD DACnC)
and 7ppm/°C (AD DACn). This performance is possible due to
the innovative design, using proprietary monolithic D/A converter
chips. Laser-trimmed thin fllm resistors provide the linearity
and wide temperature range for guaranteed monotonicity.
OLE
TE
AD DAC71/AD
DAC72
PRODUCT HIGHLIGHTS
1. The AD DAC7l and AD DACn
with 0.003% linearity error.
provide l6-bit resolution
2. The proprietary chips used in the hybrid design provide
excellent stability over temperature and improved reliability.
3. Unipolar and bipolar current and voltage output versions are
available to fill a wide range of system requirements.
4. The AD DAC71 and AD DACn are improved second source
replacements for DAC71 and DACn devices from other
manufacturers.
The AD DAC71 and AD DACn digital inputs are ITL-com-
patible. Coding is complementary straight binary (CSB) for
unipolar output versions and complementary offset binary (COB)
for bipolar output versions.
All versions are packaged in a 24-pin metal DIP. The AD DAC71,
AD DAC71H and AD DACnC are specified for operation from
0 to + 70°C, and the AD DACn is specified from - 25°C to
+ 85°C. The AD DAC7IH, AD DACn and AD DACnC are
supplied in hermetically-sealed packages.
The AD DAC71 and AD DACn are intended to serve as improved
second sources to DAC71 and DACn devices from other
manufacturers.
*Covered by Patent Numbers: 3,978,473; RE28,633;
3,803,590; 3,961,326; 4,213,806; 4,136,349.
4,020,486;
3,747,088;
~ ~-~~
SPECIFICATIONS
MODEL
DIGITAL INPUTS
Resolution
Logic Levels (TTL-Compatible)t
Logical "I"
Logical "0"
ACCURACY'
Linearity Error at 2S'C
Gain Error', Voltage
Current
Offset Error" Voltage, Unipolar
Voltage, Bipolar
Current, Unipolar
Current, Bipolar
MonotonicilY Temp. Range (14-Birs)
DRIFT (Over Specified Temp. Range)
Total Bipolar Drift (includes gain, offset,
and linearity drifl)
Voltage
'1'min to 2S'C
(@ TA
=
+ 25°C,atedpower
r
supplies nless
u
otherwiseoted)
n
MIN
AD DAC72C
TYP
MAX
MIN
AD DAC72
TYP
MAX
16
+ 5.5
+0.4
=0.003
=0.15
=0.25
'" 2.0
= 10.0
= 1.0
=5.0
+50
+2.4
+0
+5.5
+0.4
=0.003
=0.15
=0.25
=2.0
= 10.0
= 1.0
=5.0
+70
UNITS
AD
DAC71/AD
DAC71H
MIN
TYP
MAX
16
+ 2.4
+0
+5.5
+0.4
000.003
=0.1
=0.25
=2.0
=5.0
= 1.0
=5.0
+50
16
+2.4
+0
Birs
Vdc
Vdc
% ofFSR3
%
%
mV
mV
flA
flA
'C
=0.01
=0.05
=0.1
=0.05
=0.05
=0.1
=0.05
=0.05
",0.1
o
o
o
",7
25'CtoTmu
Current
TmintoTmu
TOTAL ERROR OVER TEMP. RANGEs
Voltage, Unipolar
Tminto+2S'C
+2S'CtoTmu
Voltage, Bipolar
TminlO +2S'C
+2S'CtoTmu
Current, Unipolar ('1'mlnto '1'mu)
Bipolar ('1'mintoT mu)
=7
+15
= IS
= IS
",7
'" IS
=7
+ IS
'" 15
=5
=5
+10
'" 19
",II
ppmofFSRI'C
ppmofFSRI'C
ppmofFSRI'C
OBS
TEMPERATURE COEFFICIENTS
Gain
Voltage
TminlO +2S'C
+ 2S'C to '1'mu
Current
Offset
'" IS
"'I
Voltage, Unipolar
Bipolar
Currenl, Unipolar
Bipolar
Differential LinearilY over Temperalure
Linearity Error over Temperalure
SETTLING TIME
Vollage Models(lo '" 0.003% ofFSR)
Output: 20V Step
ILSB Step'
Slew Rate
Current Models (to '" 0.003% ofFSR)7
Output: 2mA step IOn to loon Load
Ikn Load
Switching Transienl
ANALOG OUTPUT
Voltage Models
Ranges-CSB
COB
Output Currenl
OUIPUIImpedance (de)
Short Circuit Duralion
Current Models
Ranges-CSB
COB
OutPUI Impedance-Unipnlar
Bipolar
Compliance
INTERNAL REFERENCE VOLTAGE
Maximum External Current'
Temp. Coeff. of Drift
POWER SUPPLY SENSITIVITY
lJnipnlarOffset
= ISVdc
I 5Vdc
Bipolar Offsot
.IWdc
I 5V de
5
010 11O
c'c1O
5
3
20
10
5
= 15
",2
",2
1
3
500
010
'I
6.0
3.0
].5
6.0
6.3
2
,]0
",0.083
= 0.083
"'°.083
= 0.083
'" 0.071
=0.071
=0.23
",0.23
",0.100
",0.072
=0.100
",0.072
=0.24
",0.24
%ofFSR
%ofFSR
%ofFSR
%ofFSR
%ofFSR
%ofFSR
",0.071
",0.071
=0.23
=0.23
'" IS
'" 15
=2
= 10
",I
OLE
TE
= 15
",IS
= 15
",7
= IS
",10
ppmofFSRI'C
ppmofFSRI'C
ppmofFSRI'C
"'1
=2
"'1
=2
=8
",1
=10
",I
",15
"'10
=2
=2
=I
",1
ppm ofFSRI'C
ppmofFSRI'C
ppmofFSRI'C
ppmofFSRI'C
ppmofFSRI'C
ppm ofFSRI'C
5
3
20
10
5
5
3
20
10
5
flS
flS
VlflS
I
3
500
500
I
3
flS
flS
mV
010 , 10
,,10
c'c5
5
0.05
IndefinilclnCommon
()10 2
'I
6.0
3.0
IS
6.0
6.3
I ]0
6.6
'3
'10
IS
6.()
6.6
,3
',1O
Oto.. 10
'10
0.05
Indefinite In Common
Oto - 2
V
V
mA
0.05
Indefinite 10Common
n
"I
6.0
3.0
, ]0
6.3
6.6
3
,,5
mA
mA
kn
kn
V
V
mA
nnml"C
().0001
,0.0001
+
0.0001
'O.()()o1
'. 0.Q()()4
,O.Q(XJI
',0.000]
'O.()()()]
'O.00()4
'().OOOI
%nfFSRI%V,
%ofFSR/%V,
%nfFSR/% V,
% of FSRI% V,
. O.
004
0
'"O.()()()]
2-306
DIGITAL-TO-ANALOG CONVERTERS
MODEL
POWER SUPPLY SENSITIVITY
(Contmued)
Gaio
, 1SVde
I SVde
POWER SUPPLY REQUIREMENTS
DAC71172
Supply
Dram.
I 1SV de (no load)
15Vdc(noload)
I 5Vde(loglcsupply)
AD DAC71/AD DAC71H
MAX
TYI'
MIN
MIN
AD DAC72C
MAX
TYI'
MIN
AD DAC72
MAX
Tn
UNITS
.
+ 14.5.
I 4.75
0.001
+
, 0.0005
+ 15.0.
I 5.0
10
30
10
.
0.0001
15.0
0.001
.,0.001
,,0.0005
'15.5.
I 5.25
20
55
20
%ofFSR/%V,
%ofFSR/% Vs
'15.5.
I 5.25
20
55
20
. 145.
+ 4.75
. 15.0.
10
30
10
'.15.5.
15.25
20
55
20
! 14.5.
+ 4.75
,15.0.
I 5.0
10
30
10
Vde
rnA
mA
lOA
TEMPERATURE
RANGE
0
25
. 55
I 70
185
+ 100
0
25
. 55
I 70
t 85
+ 100
25
55
55
185
+ 100
; 110
"C
"C
"C
Specification
Operating (double above Drift Specs)
Storage
NOTES
.
+Vs
+VS
-Vs
'Adding<mmal CMOS h« burfm CD4009A will p""id< IIV dc CMOS inpullompatib"'IY.
'Aeeumy"
'po,',fi<d wh<n u,iog Int<mal f«db"k m""o". Cumnt OO'PUI
'pocifieation","
gumnt«d..
Ih< ,nhag< OU'PUIofanw<malopamp
using
tho internal f«dback mistol.
'FSR m<an> Full Seak Rang<and is 20V fol' IOVcongo
'Ad,u",bl< 1O'<10 with <,,<mal liim potentiom«<I.
OBS
+Vs
+Vs
'Withgamandoff"I<Ho"adiomdtowoat
25"C
"L5B is fol 14.bit «solution.
'I'awn«aguacant«d.
not te",d
"M"imum with nod<gcadation of,pocifi"Iion.
Specification> sub,<cI to chango without notic<.
AD DAC71 AND AD DAC72
'R, = 5kIlICSBJ. 10kll (COBI
OLE
TE
Vs
iV,
+V,
AD DAC71 AND AD DAC72
'R, = 5kIlICSBJ. 10klliCOBI
Figure
1.
External Adjustment and Voltage Supply Con-
nection Diagram, Current Model
ORDERING
Model
AD
AD
AD
AD
AD
AD
AD
AD
AD
AD
AD
AD
AD
AD
AD
AD
DAC7I-COB-I
DAC7I-CSB-I
DAC71H-COB-I
DAC71H-CSB-I
DAC72C-COB-I
DAC72C-CSB-I
DAC72-COB-I
DAC72-CSB-I
DAC71-COB-V
DAC71-CSB-V
DAC71H-COB-V
DAC71H-CSB-V
DAC72C-COB-V
DAC72C-CSB-V
DAC72-COB-V
DAC72-CSB-V
Output
Current
Current
Current
Current
Current
Current
Current
Current
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Input Code
Figure
2.
External Adjustment and Voltage Supply Con-
nection Diagram, Voltage Model
GUIDE
Temperature
Range
0 to
0 to
0 to
0 to
+ 70°C
+ 70°C
+ 70°C
+ 70°C
Seal
Polymer
Polymer
Hermetic
Hermetic
Package
Option.
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
DH-24D
Compo Offset Binary
Compo Straight Binary
Compo Offset Binary
Compo Straight Binary
Compo Offset Binary
Compo Straight Binary
Compo Offset Binary
Compo Straight Binary
Compo Offset Binary
Compo Straight Binary
Compo Offset Binary
Compo Straight Binary
Compo Offset Binary
Compo Straight Binary
Compo Offset Binary
Compo Straight Binary
Hermetic
0 to + 70°C
0 to + 70°C
Hermetic
- 25°C to + 85°C Hermetic
-
25°Cto + 85°C Hermetic
+ 70°C
+ 70°C
+ 70°C
+ 70°C
Polymer
Polymer
Hermetic
Hermetic
Hermetic
Hermetic
Hermetic
Hermetic
0 to
0 to
0 to
0 to
0 to + 70°C
0 to + 70°C
- 25°C to + 85°C
- 25°C to + 85°C
*SeeSection 13for package outline information.
----
--
rAr..~r..A
v
1l"i'U 1 nr.. ft\...\...UAft\...l
VI'
111~
ftU
Ul\l.;J
1
AND AD DAC72
A great deal of care must be exercised when using high resolution
converters such as the AD DAC71 and AD DAC72. Since one
least significant bit of a 16-bit converter (LSB) represents an
analog voltage of only 153 microvolts out of a IOV scale, normally
negligible error sources become significant. Series resistances of
connectors and wiring can be major contributors, as can ther-
mocouple effects. Figure 3 illustrates the connections for voltage
output versions of the AD DAC71 and AD DAC72.
AD DAC71 AND AD DAC72 CSB-V
the load to the sensed remotely. The resistance (RWI) of the
lead connecting the load to the internal feedback resistor in-
troduces a gain error equal to
~,
I\.LOAD
independent of RLOAD
and Rwz. The error contributed by RW3depends upon where
the output is measured. If the output is measured between the
top of RLoAD and pin 20 of the DAC, no error results since
RW3effectively becomes part of the load resistance.
In applications where RW3is large or large currents flow in
RW3, it is necessary to use remote sensing as shown in Figure
5.
AD DAC71 AND
AD DAC72 CSB-I
5k
Rw,
Rm
Rw,
+
RwA
RWAO
+
---0
RWAD
VWAD
(REMOTE
ANALOG GROUND)
RA + RwA
~
-
}
VOUT
5k + Rw,
Rw,
TO POWER COMMON
Rw,
OBS
TO OTHER
ANALOG
CIRCUITS
TO
POWER
SUPPLY
RETURN
Figure
5.
Useof
Output
Amplifier as Subtractor for Remote
Ground Sensing
This circuit uses the output amplifier as a subtractor stage. Any
spurious voltage developed across RW3becomes a common
mode voltage and its error contribution is reduced by the common
mode rejection of the op amp.
Figure
3.
AD DAC71 and AD DAC72 Connection Diagram
(Voltage Models)
In this circuit, the analog output voltage is accurately developed
between pin 17 and pin 20 of the DAC. The voltage measured
at the load will be inaccurate if there is significant resistance in
the wiring (and any connectors) between the DAC and the load.
If the load resistance is constant, the effects of RWI and RW2
can be treated as a simple gain error, and can be trimmed out.
However, if RL is variable, then RWI and RW2should be re-
duced to a value less than RL2~IN. This will reduce the effect of
the wiring resistances to a gain error of less than lLSB. The
AD DAC71 and AD DAC72 are rated at an output current of
SmA which translates to a minimum load resistance of 2kn.
Thus wiring resistances should be held to a maximum of 30
milliohms. This corresponds to approximately six inches of #28
wire or a six inch long printed circuit track 0.050 inches wide.
The current output versions of the AD DAC71 and AD DAC72
use an external operational amplifier to convert the output current
to an output voltage. The recommended configuration is shown
in Figure 4. Notice that this configuration permits the voltage
at
AD DAC7' AND
AD DAC72 CSB-I
OLE
TE
RWAD
In the circuits of both Figure 4 and Figure 5, RW2'Seffect is
negligible since it is inside the loop of the amplifier. If current
boosting is required in order to drive heavy loads, a suitable
booster stage can be inserted between the amplifier's output and
the load. Since the loop is closed from the load end, offsets and
other errors induced by the booster are eliminated.
Rw,
5kU
R,
r--
It is also important to minimize thermocouple effects in circuitry
using the AD DAC71 and AD DAC72. Recalling that lLSB of
a 16 bit, 10 volt scale converter is only 153 microvolts, a stray
uncompensated thermocouple can introduce several LSBs of
offset in response to minor changes in ambient temperature.
Any part of a circuit which includes a junction between two
dissimilar metals forms a thermocouple. Such junctions include
connectors, sockets, and any soldered connections. The solution
to thermocouple errors is to insure that every junction is cancelled
by an identical, but opposite, junction at the same temperature.
While this is often automatically accomplished (for example, in
a connector carrying both signal and return leads), careful attention
should be given to the physical layout of circuits using the AD
DAC71 and AD DAC72.
Rw,
Rw,
OR.
R.
~ 2.7kU
~ 1.8kU
FOR CSB
FOR COB
TO OTHER
ANALOG
CIRCUITRY
TO POWER
SUPPLY
COMMON
l~'
Another source of signal degradation in high-resolution converter
circuits is magnetically-coupled interference from stray fields.
Signal and return leads should be arranged in a way which
minimizes both length and the total cross-section area of the
loop. Of course, high resolution circuits should be located as far
as possible from any sources of electromagnetic interference,
including power transformers, digital logic and electromechanical
devices.
Figure
4.
Connections
Output Versions
for AD DAC71 and AD DAC72 Current
2-308
DlGITAL- TO-ANALOG CONVERTERS
--
DH-24D
24-Lead Metal Platform DIP
24
13
OBS
SEE
NOTE
1
"
1
j4
D
111
A
.1
cpb
~1
...fj.-
..je~
MILLIMETERS
MIN
MAX
6.35
0.41
0.51
35.18
20.57
15.00
15.50
2.54 BSC
3.56
5.33
OLE
TE
12
~
FE===]
I-
E,
+
cpb
.f
SYMBOL
A
cpb
D
E
INCHES
MIN
MAX
0.250
0.016
0.020
1.385
0.810
0.590
0.610
0.100BSC
0.140
0.210
NOTES
NOTES
located at lead one.
2. The basic pin spacing is 0.100" (2.54mm) between
centerlines.
3. E, shall be measured at the centerline of the leads.
3
2
1.
Index
area; a colored bead or identification mark is
E,
e
L,
II
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