K4S641632C
1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
•
•
•
•
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S641632C is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 16
bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
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•
•
•
•
ORDERING INFORMATION
Part No.
K4S641632C-TC/L60
K4S641632C-TC/L70
K4S641632C-TC/L75
K4S641632C-TC/L80
K4S641632C-TC/L1H
K4S641632C-TC/L1L
K4S641632C-TC/L10
Max Freq.
166MHz(CL=3)
143MHz(CL=3)
133MHz(CL=3)
125MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
66MHz(CL=3&2)
LVTTL
54
TSOP(II)
Interface Package
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select
1M x 16
1M x 16
1M x 16
1M x 16
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
K4S641632C
PIN CONFIGURATION
(Top view)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
N.C/RFU
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
SS
CMOS SDRAM
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
11
, Column address : CA
0
~ CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A
0
~ A
11
BA
0
~ BA
1
RAS
CAS
WE
L(U)DQM
DQ
0
~
15
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C/RFU
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No connection
/reserved for future use
K4S641632C
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current (Inputs)
Input leakage current (I/O pins)
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
IL
Min
3.0
2.0
-0.3
2.4
-
-1
-1.5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
1
1.5
Unit
V
V
V
V
V
uA
uA
Note
5
1
2
I
OH
= -2mA
I
OL
= 2mA
3
3,4
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
5. The VDD condition of K4S641632C-60 is 3.135V~3.6V.
CAPACITANCE
Clock
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
= 1.4V
±
200 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.5
2.5
2.5
4.0
Max
4.0
5.0
5.0
6.5
Unit
pF
pF
pF
pF
RAS, CAS, WE, CS, CKE, L(U)DQM
Address
DQ
0
~ DQ
15
K4S641632C
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70°C)
Parameter
Symbol
Test Condition
Burst length = 1
t
RC
≥
t
RC
(min)
I
OL
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 15ns
CAS
Latency
CMOS SDRAM
Version
-60 -70 -75 -80 -1H -1L -10
85
75
75
75
1
1
12
70
70
65
Unit Note
Operating current
(One bank active)
Precharge standby current
in power-down mode
I
CC1
I
CC2
P
mA
I
CC2
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
mA
Precharge standby current
in non power-down mode
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
NS
Input signals are stable
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 15ns
mA
6
2
2
20
10
3
2
130 130 130 115
-
145
C
L
90
90
90
125
1
450
90
90
90
85
90
mA
85
110 mA
mA
uA
2
3
4
1
mA
mA
Active standby current in
power-down mode
I
CC3
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
N
I
CC3
NS
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
OL
= 0 mA
Page burst
2Banks activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
mA
Active standby current in
non power-down mode
(One bank active)
Operating current
(Burst mode)
Refresh current
Self refresh current
I
CC4
I
CC5
I
CC6
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S641632C-TC**
4. K4S641632C-TL**
K4S641632C
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
3.3V
CMOS SDRAM
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Vtt = 1.4V
Unit
V
V
ns
V
1200Ω
Output
870Ω
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
50pF
*Note1
Output
Z0 = 50Ω
50Ω
50pF
*Note1
(Fig. 1) DC output load circuit
Note :
1. The DC/AC test Output Load of K4S641632C-60 is 30pF.
2. The VDD condition of K4S641632C-60 is 3.135V~3.6V.
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col. address Delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output
data
Symbol
-60
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RDL
(min)
t
CDL
(min)
t
BDL
(min)
t
CCD
(min)
60
6
68
7
68
7
12
18
18
42
-70
14
20
20
48
-75
14
20
20
48
Version
-80
16
20
20
48
100
68
8
1
1
1
2
1
70
10
70
10
80
12
-1H
20
20
20
50
-1L
20
20
20
50
-10
20
24
24
50
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
ea
1
2
2
2
3
4
Unit
Not
e
1
1
1
1
CAS latency=3
CAS latency=2
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
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