DS92LV3242 datasheet, PDF - EEWORLD Datasheet

DS92LV3242: Description20-85 MHz 32-Bit Channel Link II Serializer/Deserializer; File Size2MB，31 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

Stay tuned Compare

DS92LV3242 Overview

20-85 MHz 32-Bit Channel Link II Serializer/Deserializer

DS92LV3242 Related Products

	DS92LV3242	DS92LV3241	DS92LV3241TVS	DS92LV3241TVSX	DS92LV3242TVS	DS92LV3242TVSX
Description	20-85 MHz 32-Bit Channel Link II Serializer/Deserializer	20-85 MHz 32-Bit Channel Link II Serializer/Deserializer	20-85 MHz 32-Bit Channel Link II Serializer/Deserializer	20-85 MHz 32-Bit Channel Link II Serializer/Deserializer	20-85 MHz 32-Bit Channel Link II Serializer/Deserializer	20-85 MHz 32-Bit Channel Link II Serializer/Deserializer
Is it Rohs certified?	-	-	incompatible	incompatible	incompatible	incompatible
Maker	-	-	National Semiconductor（TI ）	National Semiconductor（TI ）	National Semiconductor（TI ）	National Semiconductor（TI ）
package instruction	-	-	TFQFP, TQFP64,.47SQ	TFQFP, TQFP64,.47SQ	TFQFP, TQFP64,.47SQ	TFQFP, TQFP64,.47SQ
Reach Compliance Code	-	-	compli	compli	compli	compli
ECCN code	-	-	EAR99	EAR99	EAR99	EAR99
Other features	-	-	IT ALSO NEED 1.8V I/O SUPPLY	IT ALSO NEED 1.8V I/O SUPPLY	IT ALSO NEED 1.8V I/O SUPPLY	IT ALSO NEED 1.8V I/O SUPPLY
Input properties	-	-	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL
Interface integrated circuit type	-	-	LINE DRIVER	LINE DRIVER	LINE RECEIVER	LINE RECEIVER
Interface standards	-	-	GENERAL PURPOSE	GENERAL PURPOSE	GENERAL PURPOSE	GENERAL PURPOSE
JESD-30 code	-	-	S-XQFP-G64	S-XQFP-G64	S-XQFP-G64	S-XQFP-G64
JESD-609 code	-	-	e0	e0	e0	e0
length	-	-	10 mm	10 mm	10 mm	10 mm
Number of functions	-	-	4	4	4	4
Number of terminals	-	-	64	64	64	64
Maximum operating temperature	-	-	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-	-	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	-	-	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	-	-	TFQFP	TFQFP	TFQFP	TFQFP
Encapsulate equivalent code	-	-	TQFP64,.47SQ	TQFP64,.47SQ	TQFP64,.47SQ	TQFP64,.47SQ
Package shape	-	-	SQUARE	SQUARE	SQUARE	SQUARE
Package form	-	-	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	-	-	1.8/3.3,3.3 V	1.8/3.3,3.3 V	3.3 V	3.3 V
Certification status	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	-	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage	-	-	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage	-	-	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage	-	-	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	-	-	YES	YES	YES	YES
Temperature level	-	-	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	-	-	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	-	-	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	-	-	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	-	-	10 mm	10 mm	10 mm	10 mm

Recommended Resources

Anti-shake circuit using CMOS NOR gate

The fourth Y-△ step-down starting circuit with arc flashover short circuit protection function

LA5511 principle block diagram and typical application circuit

NE542 sound recording and playback compensation amplifier using operational amplifier

4.194304MHZ reference clock circuit diagram

875p computer motherboard circuit diagram_080

crc16 source code sharing: // Copyright 2007 Altera Corporation. All rights reserved. // Altera products are protected under numerous U.S. and foreign patents, // maskwork rights, copyrights and other intellectual property laws...; eeleader FPGA/CPLD

[FPGA Design Problem] Three signal edges in the sensitivity list in Verilog: Data is sent when the rising edge of clock clk and signal A is high at the same time, but signal A has a fixed cycle (maintaining the high of 8 clocks), but when the rising edge of clock clk happens, ...; eeleader FPGA/CPLD

Newbie's question: What's wrong with the Baudrate calculation of my P89V51RD2?: Crystal: 32MHz Use timer2 as Baudrate Set TMOD = 0x21; // Use mode3 According to the formula Baud rate = fosc / (16 × (65536(RCAP2H, RCAP2L))) ---------------------------------------------------------...; liluo44 51mcu

I have used 430 to make DS18B20. Please help me modify the program.: Anyone who has used 430 to work on DS18B20, please help me modify the program. Below is the main function and the main parts of 18B20. Do you have any other questions? void main() { WDTCTL = WDTPW + W...; nwx8899 Microcontroller MCU

Data Acquisition Device Based on FPGA: [i=s]This post was last edited by paulhyde on 2014-9-15 04:13[/i] FPGA-based data acquisition deviceAbstract: A high-speed data acquisition system with FPGA as the core logic control module is designe...; napianlvse Electronics Design Contest

lm3s serial port interrupt receiving timeout interrupt is not triggered: I originally planned to judge the reception end flag in the timeout interrupt. If I set the serial port receiving FIFO to a depth of 6/8 and set the receiving FIFO interrupt and receiving timeout inte...; usthanos Microcontroller MCU

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components