SIW3500 datasheet, PDF - EEWORLD Datasheet

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SIW3500: DescriptionULTIMATEBLUE; File Size190KB，18 Pages; ManufacturerRF Micro Devices (Qorvo)

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SIW3500 Overview

ULTIMATEBLUE

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Preliminary

Features

CLK_REQ_OUT

SiW3500

ULTIMATEBLUE

ADDRESS BUS

• RF System on Chip (SoC) for

Bluetooth wireless technology

combining a 2.4 GHz transceiver,

baseband processor, and protocol

stack ROM.

• Bluetooth specification V1.2 qualified

including mandatory and optional

functions such as AFH and eSCO.

• Manufactured using standard

0.18-micron CMOS process

technology.

• UART based Host Control Interface

(HCI) transport layer supports

standard and 3-wire modes.

• Direct conversion RF architecture

improves receiver-blocking

performance.

• I/O voltage supply can range from

1.62 V to 3.63 V.

• -85 dBm receiver sensitivity and

+2 dBm transmitter power typical

performance specifications.

• Integrated analog and digital voltage

regulators simplify system design.

• 50

Ω

RF I/O does not need any

additional external impedance

matching components.

• Flexible reference clock source

options including crystal or direct

input from the host platform.

• Internal temperature compensated

transmitter and receiver circuits

deliver consistent performance from

-40° to +85°C.

• On-chip ROM software storage with

patch capability.

RF_I/O

PLL

Control

Clock Distribution

LNA

Voltage Regulators and

Power Distribution

Optional flash interface

ADC

Internal

50-Ohm

Match

Network

ADC

PLL

Synthesizer

Power

Control

DRIVER

DAC

Aux ADC

DAC

GFSK

Modem

Bluetooth

Link

Controller

ARM7TDMI®

Processor

CS, OE and WE

UART

Multi Function

I/Os

Audio CODEC

Interface

CLK_REQ_IN

XTAL_P/CLK

VBATT_ANA

CHG_PUMP

VBATT_DIG

Data SRAM

Firmware ROM

Block Diagram

Product Description

The UltimateBlue SiW3500™ is a RF System On Chip (SoC) that combines

a 2.4 GHz transceiver, baseband processor, and protocol stack software for

Bluetooth® wireless technology. Due to its low power CMOS process, the

SiW3500 is ideally suited for applications such as mobile phones, audio

headsets, and other embedded products.

The SiW3500 integrates an ARM7TDMI processor for software execution

from either internal ROM or external FLASH memory. The standard

SiW3500 ROM contains the Bluetooth lower layer stack software including

the HCI transport driver.

The SiW3500 is packaged in a 6 x 6 Pb-Free 96-VFBGA that meets RoHS

(Green) requirements. Known Good Die (KGD) is available for special

applications.

Applications

• Mobile phones and smart phones.

• Bluetooth audio headset.

• Bluetooth hands-free kit.

Ordering Information

SiW3500

UltimateBlue

Optimum Technology Matching® Applied

Si BJT

Si Bi-CMOS

GaInP/HBT

GaAs HBT

SiGe HBT

GaN HEMT

GaAs MESFET

Si CMOS

SiGe Bi-CMOS

RF Micro Devices, Inc.

7628 Thorndike Road

Greensboro, NC 27409, USA

Tel (336) 664 1233

Fax (336) 664 0454

http://www.rfmd.com

60 0066 R00Hrf SiW3500 Radio Processor DS

November 8, 2004

DATA BUS

VCC_OUT

VBB_OUT

XTAL_N

VTUNE

VDD_P

14-37

SiW3500

Radio Features

Preliminary

• RF System on Chip (SoC) for Bluetooth wireless technology combining a 2.4 GHz transceiver, baseband processor,

and protocol stack ROM.

• Bluetooth specification V1.2 qualified including mandatory and optional functions such as AFH and eSCO.

• Manufactured using standard 0.18 m CMOS process technology.

• UART based Host Control Interface (HCI) transport layer supports standard and 3-wire modes.

•

Direct conversion RF architecture improves receiver-blocking performance.

• I/O voltage supply can range from 1.62 V to 3.63 V.

• -85 dBm receiver sensitivity and +2 dBm transmitter power typical performance specifications.

• Integrated analog and digital voltage regulators simplify system design.

• 50

Ω

RF I/O does not need any additional external impedance matching components.

•

Flexible reference clock source options including crystal or direct input from the host platform.

Internal temperature compensated transmitter and receiver circuits deliver consistent performance from -40° to

+85°C.

On-chip ROM software storage with patch capability.

Baseband Features

• Hardware based GFSK MODEM and packet processing contributes to lower system current consumption with

minimal software overhead.

• ARM7TDMI processor efficiently executes all protocol stack and application software.

• Software execution from either internal ROM or external FLASH memory. The SiW3500 features a ROM patch

mechanism that allows substituting small portions of ROM code with code either downloaded from the host or stored

in external EEPROM.

• Extensive multi function I/Os allow flexible product configurations.

• Auxiliary analog-to-digital converter (ADC) is available for applications such as battery level detection.

Standard Protocol Stack Features

• Full-featured lower layer Bluetooth protocol stack software up to the host interface (HCI).

• Bluetooth 1.2 qualified including mandatory and optional features such as AFH, extended SCO, faster connections,

and LMP improvements.

• Full Bluetooth connection capabilities with support for piconet and scatternet modes and device scanning during SCO

connection.

• Able to establish up to 3 SCO connections simultaneously.

• Supports low power connection states such as hold, sniff, and park modes with selectable sniff intervals.

• Full support of Bluetooth test modes for use during production.

• Verified HCI command level compatibility with multiple upper layer stack software.

Additional Protocol Stack Features

• Proprietary channel assessment algorithm provides fast and accurate determination of occupied channel for use in

AFH mode.

• In addition to AFH, UltimateBlue Coexistence Technology is part of the baseline protocol stack. UltimateBlue

coexistence minimizes interference to 802.11b/g products.

• The Channel Quality Driven Data Rate (CQDDR) feature optimizes data transfer in noisy or weak signal

environments.

• Full selection of upper layer protocol stack software and profiles available for license and customization.

14-38

60 0066 R00Hrf SiW3500 Radio Processor DS

Preliminary

SiW3500

EEPROM is not required for configurations with external flash. The EEPROM is the non-volatile memory (NVM) in the

system and contains the system configuration parameters such as the Bluetooth device address, the CODEC type, as

well as other parameters. These default parameters are set at the factory, and some parameters will change depending

on the system configuration. Optionally, the memory parameters can be downloaded from the host processor at boot up

eliminating the need for EEPROM. Please consult the Application Support team for details. The EEPROMs should have

a serial I

C interface with a minimum size of 2 Kbits and 16-byte page write buffer capabilities.

General System Requirements

System Reference Clock

The SiW3500 chip can use either an external crystal or a reference clock as the system clock input. A partial list of

supported frequencies (in MHz) includes: 9.6, 12, 12.8, 13, 14.4, 15.36, 16, 16.8, 19.2, 19.68, 19.8, 26, 32, 38.4, and 48.

For other frequencies, please contact Applications Support. The system reference crystal/clock must have an accuracy

of ±20 PPM or better to meet the Bluetooth specification.

Low Power Clock

For the Bluetooth low power clock, a 32.768 kHz crystal can be used to drive the SiW3500 oscillator circuit, or alterna-

tively, a 32.768 kHz reference clock signal can be used instead of a crystal. If the lowest power consumption is not

required during low-power modes such as sniff, hold, park, and idle modes, the 32.768 kHz crystal may be omitted in the

design.

If the 32.768 kHz clock source is used, the clock source should be connected to the CLK32_IN pin and must meet the

following requirements:

• For AC-coupled via 100 pF or greater (peak-to-peak voltage):

400 mV

P-P

< CLK32_IN < V

DD_C

• For DC-coupled:

CLK32_IN minimum peak voltage < V

CLK32_IN maximum peak voltage > V

Where V

= 0.3 * V

DD_C

Where V

= 0.7 * V

DD_C

• For both cases, the signal is not to exceed:

-0.3 V < CLK32_IN < V

DD_C

+ 0.3 V

Power Supply Description

The SiW3500 operates at 1.8 V core voltage for internal analog and digital circuits. The chip has internal analog and

digital voltage regulators simplifying power supply requirements to the chip. The internal voltage regulators can be

supplied directly from a battery or from other system voltage sources. Optionally, the internal regulators can be by-

passed if 1.8 V regulated source is available on the system.

Function

Regulator input pin

Regulator output pin

Internal Analog Regulator

BATT_ANA

= 2.3 to 3.63 V

CC_OUT

= 1.8 V

Internal Digital Regulator

BATT_DIG

= 2.3 to 3.63 V

DD_C

= 1.8 V

Internal

Regulator Used

Function

Circuit voltage supply pin

Analog Core Circuits

= 1.8 V

Digital Core Circuits

DD_C

= 1.8 V

Internal Regulator Bypassed

Note:

Both regulators can be bypassed if external regulation is desired. When bypassing the analog regulator, the VBATT_ANA and VCC_OUT pins

must be tied together and the external analog voltage (1.8 V) should be applied to the VBATT_ANA pin. When bypassing the digital regulator, the

VBATT_DIG pin should be left unconnected and the external digital voltage (1.8 V) should be applied to VBB_OUT pin.

The power for the I/Os is taken from two separate sources (V

DD_P

and V

DD_P_ALT

). They can range from 1.62 to 3.63

60 0066 R00Hrf SiW3500 Radio Processor DS

14-41

SIW3500 Related Products

	SIW3500	SiW3500DIF1	SiW3500DIF1-T13	SIW3500GIG1	SIW3500GIG1-T13
Description	ULTIMATEBLUE	ULTIMATEBLUE	ULTIMATEBLUE	ULTIMATEBLUE	ULTIMATEBLUE

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