Preliminary
0
Features
CLK_REQ_OUT
SiW3500
ULTIMATEBLUE
ADDRESS BUS
• RF System on Chip (SoC) for
Bluetooth wireless technology
combining a 2.4 GHz transceiver,
baseband processor, and protocol
stack ROM.
• Bluetooth specification V1.2 qualified
including mandatory and optional
functions such as AFH and eSCO.
• Manufactured using standard
0.18-micron CMOS process
technology.
• UART based Host Control Interface
(HCI) transport layer supports
standard and 3-wire modes.
• Direct conversion RF architecture
improves receiver-blocking
performance.
• I/O voltage supply can range from
1.62 V to 3.63 V.
• -85 dBm receiver sensitivity and
+2 dBm transmitter power typical
performance specifications.
• Integrated analog and digital voltage
regulators simplify system design.
• 50
Ω
RF I/O does not need any
additional external impedance
matching components.
• Flexible reference clock source
options including crystal or direct
input from the host platform.
• Internal temperature compensated
transmitter and receiver circuits
deliver consistent performance from
-40° to +85°C.
• On-chip ROM software storage with
patch capability.
RF_I/O
PLL
Control
Clock Distribution
LNA
Voltage Regulators and
Power Distribution
Optional flash interface
ADC
0
90
Internal
50-Ohm
Match
Network
ADC
PLL
Synthesizer
Power
Control
0
90
DRIVER
DAC
Aux ADC
DAC
GFSK
Modem
Bluetooth
Link
Controller
ARM7TDMI®
Processor
CS, OE and WE
UART
Multi Function
I/Os
Audio CODEC
Interface
CLK_REQ_IN
XTAL_P/CLK
VBATT_ANA
CHG_PUMP
VBATT_DIG
Data SRAM
Firmware ROM
Block Diagram
Product Description
The UltimateBlue SiW3500™ is a RF System On Chip (SoC) that combines
a 2.4 GHz transceiver, baseband processor, and protocol stack software for
Bluetooth® wireless technology. Due to its low power CMOS process, the
SiW3500 is ideally suited for applications such as mobile phones, audio
headsets, and other embedded products.
The SiW3500 integrates an ARM7TDMI processor for software execution
from either internal ROM or external FLASH memory. The standard
SiW3500 ROM contains the Bluetooth lower layer stack software including
the HCI transport driver.
The SiW3500 is packaged in a 6 x 6 Pb-Free 96-VFBGA that meets RoHS
(Green) requirements. Known Good Die (KGD) is available for special
applications.
Applications
• Mobile phones and smart phones.
• Bluetooth audio headset.
• Bluetooth hands-free kit.
Ordering Information
SiW3500
UltimateBlue
Optimum Technology Matching® Applied
Si BJT
Si Bi-CMOS
GaInP/HBT
GaAs HBT
SiGe HBT
GaN HEMT
GaAs MESFET
Si CMOS
SiGe Bi-CMOS
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
60 0066 R00Hrf SiW3500 Radio Processor DS
November 8, 2004
DATA BUS
VCC_OUT
VBB_OUT
XTAL_N
VTUNE
VDD_P
14-37
SiW3500
Radio Features
Preliminary
• RF System on Chip (SoC) for Bluetooth wireless technology combining a 2.4 GHz transceiver, baseband processor,
and protocol stack ROM.
• Bluetooth specification V1.2 qualified including mandatory and optional functions such as AFH and eSCO.
• Manufactured using standard 0.18 m CMOS process technology.
• UART based Host Control Interface (HCI) transport layer supports standard and 3-wire modes.
•
Direct conversion RF architecture improves receiver-blocking performance.
• I/O voltage supply can range from 1.62 V to 3.63 V.
• -85 dBm receiver sensitivity and +2 dBm transmitter power typical performance specifications.
• Integrated analog and digital voltage regulators simplify system design.
• 50
Ω
RF I/O does not need any additional external impedance matching components.
•
•
•
Flexible reference clock source options including crystal or direct input from the host platform.
Internal temperature compensated transmitter and receiver circuits deliver consistent performance from -40° to
+85°C.
On-chip ROM software storage with patch capability.
Baseband Features
• Hardware based GFSK MODEM and packet processing contributes to lower system current consumption with
minimal software overhead.
• ARM7TDMI processor efficiently executes all protocol stack and application software.
• Software execution from either internal ROM or external FLASH memory. The SiW3500 features a ROM patch
mechanism that allows substituting small portions of ROM code with code either downloaded from the host or stored
in external EEPROM.
• Extensive multi function I/Os allow flexible product configurations.
• Auxiliary analog-to-digital converter (ADC) is available for applications such as battery level detection.
Standard Protocol Stack Features
• Full-featured lower layer Bluetooth protocol stack software up to the host interface (HCI).
• Bluetooth 1.2 qualified including mandatory and optional features such as AFH, extended SCO, faster connections,
and LMP improvements.
• Full Bluetooth connection capabilities with support for piconet and scatternet modes and device scanning during SCO
connection.
• Able to establish up to 3 SCO connections simultaneously.
• Supports low power connection states such as hold, sniff, and park modes with selectable sniff intervals.
• Full support of Bluetooth test modes for use during production.
• Verified HCI command level compatibility with multiple upper layer stack software.
Additional Protocol Stack Features
• Proprietary channel assessment algorithm provides fast and accurate determination of occupied channel for use in
AFH mode.
• In addition to AFH, UltimateBlue Coexistence Technology is part of the baseline protocol stack. UltimateBlue
coexistence minimizes interference to 802.11b/g products.
• The Channel Quality Driven Data Rate (CQDDR) feature optimizes data transfer in noisy or weak signal
environments.
• Full selection of upper layer protocol stack software and profiles available for license and customization.
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60 0066 R00Hrf SiW3500 Radio Processor DS
Preliminary
SiW3500
ROM Features
SiW3500
HCI
SiW3500
Headset
Protocol Stack
Lower stack up to HCI
UltimateBlue Coexistence
Upper Stack (L2CAP, SDP, RFCOMM)
Programming Interface (API)
[
[
–
–
[
[
[
[
[
[
Profiles
Headset Profile (HSP)
Hands Free Profile (HFP)
–
–
[
= Included in SiW3500 ROM
External System Interfaces
Host HCI Transport (UART)
The high speed UART interface provides the physical transport between the SiW3500 and the application host for the
transfer of Bluetooth data compliant with the Bluetooth specification. The table below shows the supported configura-
tions. The default baud rate is 115,200 bps and can be set depending on the product.
SiW3500 Radio Processor HCI UART Parameters
Number of data bits
Parity bit
Stop bit
Flow control
Host flow-off response requirement from the SiW3500
SiW3500 IC flow-off response requirement from host
Supported baud rates
8
No parity
1 stop bit
RTS/CTS
8 bytes
2 bytes
9.6k, 19.2k, 38.4k, 57.6k, 115.2k, 230.4k, 460.8k, 500k, 921.6k,
1M, 1.5M, 2M
Required Host Setting
Host HCI Transport (3-Wire UART)
To reduce the number of signals and to increase the reliability of the HCI UART interface, a 3-wire UART protocol is
available in the SiW3500. The protocol is compliant with the Bluetooth specification H:5 transport and backwards
compatible with the BCSP 3-wire UART protocol. Selection between H:4 UART, H:5 UART, and BCSP UART is done
automatically by the SiW3500.
SiW3500 Radio Processor HCI 3-Wire UART Parameters
Number of data bits
Parity bit
Stop bit
Error detection
Sleep modes
8
Even
1 stop bit
SLIP and checksum
Shallow and deep
Required Host Setting
Audio Codec Interface
The SiW3500 supports direct interface to an external audio CODEC or PCM host device. The interface provides the
following configurations:
•
•
•
•
Standard PCM clock rates from 64 kHz to 2.048 MHz with multi-slot handshakes and synchronization.
Supports either master or slave mode.
Supports any PCM data size up to 16 bits.
Compatible with Motorola SSI mode.
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60 0066 R00Hrf SiW3500 Radio Processor DS
SiW3500
Preliminary
• Configuration of the CODEC interface is done by the firmware during boot-up by reading non-volatile memory (NVM)
parameters.
Multi-function I/Os (MFPs)
Up to 8 (eight) multi-function I/O ports are available in the SiW3500. The table below identifies the I/Os and their usage.
Multi Function I/O Number
MFP[0]
MFP[1]
MFP[2]
MFP[3]
MFP[4]
MFP[5]
MFP[6]
MFP[7]
Possible Usage Configuration
General purpose.
CLOCK_REQ_IN, HOST_WAKEUP, General purpose.
Address A[18], SYNC_CLOCK, AUX_RTS, General purpose.
FREQ_SEL[3], SYNC_DATA, General purpose.
FREQ_SEL[1], General purpose.
FREQ_SEL[2], General purpose.
AUX_RXD, General purpose.
AUX_CTS, TX_RX_SWITCH, General purpose.
External Memory Interface
The SiW3500 does not require additional memory for standard below HCI protocol functions. An external memory
interface is available for execution of protocol stack software from FLASH memory if desired. If external FLASH memory
will be used, the read access time of the device must be 100 ns or less.
Auxiliary UART
The SiW3500 can be configured and enabled with an auxiliary UART port. This UART port can be used for debug
depending on the application software.
Signal
AUX_TXD
AUX_RXD
AUX_CTS
AUX_RTS
TX Data
RX Data
Clear To Send
Request To Send
Description
External Power Amplifier Interface
The SiW3500 supports the use of an external power amplifier for +20 dBm designs. When enabled, these signals
provide an integrated interface for the control of an external PA.
Signal
IDAC
TX_RX_SWITCH
Description
Power control to external PA. This output provides a variable current source
that can be used to control the external PA. Leave unconnected if not used
Output signal used to indicate the state of the radio. This could be used as a
direction control for the PA. The polarity is programmable with the default set
as: Low = Transmit; High = Receive.
Power Management
The HOST_WAKEUP and EXT_WAKE signals are used for power management control of the SiW3500.
HOST_WAKEUP is an output signal used to indicate Bluetooth activity to the host. EXT_WAKE is an input signal used
by the host to wake up the SiW3500 from sleep mode.
For control of the reference clock source, CLOCK_REQ_IN and CLOCK_REQ_OUT can be made available to turn on/off
an external reference clock source.
General-Purpose Analog to Digital Converter (ADC)
The SiW3500 incorporates a general-purpose ADC that can be enabled to sample external analog voltage. The ADC
has an 8-bit resolution.
External EEPROM Controller and Interface
This interface is intended for communication to an optional EEPROM when using the SiW3500 in ROM mode. The
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60 0066 R00Hrf SiW3500 Radio Processor DS
Preliminary
SiW3500
EEPROM is not required for configurations with external flash. The EEPROM is the non-volatile memory (NVM) in the
system and contains the system configuration parameters such as the Bluetooth device address, the CODEC type, as
well as other parameters. These default parameters are set at the factory, and some parameters will change depending
on the system configuration. Optionally, the memory parameters can be downloaded from the host processor at boot up
eliminating the need for EEPROM. Please consult the Application Support team for details. The EEPROMs should have
a serial I
2
C interface with a minimum size of 2 Kbits and 16-byte page write buffer capabilities.
General System Requirements
System Reference Clock
The SiW3500 chip can use either an external crystal or a reference clock as the system clock input. A partial list of
supported frequencies (in MHz) includes: 9.6, 12, 12.8, 13, 14.4, 15.36, 16, 16.8, 19.2, 19.68, 19.8, 26, 32, 38.4, and 48.
For other frequencies, please contact Applications Support. The system reference crystal/clock must have an accuracy
of ±20 PPM or better to meet the Bluetooth specification.
Low Power Clock
For the Bluetooth low power clock, a 32.768 kHz crystal can be used to drive the SiW3500 oscillator circuit, or alterna-
tively, a 32.768 kHz reference clock signal can be used instead of a crystal. If the lowest power consumption is not
required during low-power modes such as sniff, hold, park, and idle modes, the 32.768 kHz crystal may be omitted in the
design.
If the 32.768 kHz clock source is used, the clock source should be connected to the CLK32_IN pin and must meet the
following requirements:
• For AC-coupled via 100 pF or greater (peak-to-peak voltage):
400 mV
P-P
< CLK32_IN < V
DD_C
• For DC-coupled:
CLK32_IN minimum peak voltage < V
IL
CLK32_IN maximum peak voltage > V
IH
Where V
IL
= 0.3 * V
DD_C
Where V
IH
= 0.7 * V
DD_C
• For both cases, the signal is not to exceed:
-0.3 V < CLK32_IN < V
DD_C
+ 0.3 V
Power Supply Description
The SiW3500 operates at 1.8 V core voltage for internal analog and digital circuits. The chip has internal analog and
digital voltage regulators simplifying power supply requirements to the chip. The internal voltage regulators can be
supplied directly from a battery or from other system voltage sources. Optionally, the internal regulators can be by-
passed if 1.8 V regulated source is available on the system.
Function
Regulator input pin
Regulator output pin
Internal Analog Regulator
V
BATT_ANA
= 2.3 to 3.63 V
V
CC_OUT
= 1.8 V
Internal Digital Regulator
V
BATT_DIG
= 2.3 to 3.63 V
V
DD_C
= 1.8 V
Internal
Regulator Used
Function
Circuit voltage supply pin
Analog Core Circuits
V
CC
= 1.8 V
Digital Core Circuits
V
DD_C
= 1.8 V
Internal Regulator Bypassed
Note:
Both regulators can be bypassed if external regulation is desired. When bypassing the analog regulator, the VBATT_ANA and VCC_OUT pins
must be tied together and the external analog voltage (1.8 V) should be applied to the VBATT_ANA pin. When bypassing the digital regulator, the
VBATT_DIG pin should be left unconnected and the external digital voltage (1.8 V) should be applied to VBB_OUT pin.
The power for the I/Os is taken from two separate sources (V
DD_P
and V
DD_P_ALT
). They can range from 1.62 to 3.63
60 0066 R00Hrf SiW3500 Radio Processor DS
14-41
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